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data sheet november 2006 orca series 3c and 3t field-programmable gate arrays features high-performance, cost-effective, 0.35 ? (or3c) and 0.3 ? (or3t) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in 0.3 ?). same basic architecture as lower-voltage, advanced process technology series 3 architectures. (see orca series 3l fpga documentation.) up to 186,000 usable gates. up to 342 user i/os. (or3txxx i/os are 5 v tolerant to allow interconnection to both 3.3 v and 5 v devices, selectable on a per-pin basis.) pin selectable i/o clamping diodes provide 5 v or 3.3 v pci compliance and 5 v tolerance on or3txxx devices. twin-quad programmable function unit (pfu) architec- ture with eight 16-bit look-up tables (luts) per pfu, organized in two nibbles for use in nibble- or byte-wide functions. allows for mixed arithmetic and logic functions in a single pfu. nine user registers per pfu, one following each lut, plus one extra. all have programmable clock enable and local set/reset, plus a global set/reset that can be dis- abled per pfu. flexible input structure (fins) of the pfus provides a routability enhancement for luts with shared inputs and the logic ?xibility of luts with independent inputs. fast-carry logic and routing to adjacent pfus for nibble-, byte-wide, or longer arithmetic functions, with the option to register the pfu carry-out. softwired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu for up to 40% speed improvement. supplemental logic and interconnect cell (slic) pro- vides 3-statable buffers, up to 10-bit decoder, and pa l *- like and-or with optional invert in each programma- ble logic cell (plc), with over 50% speed improvement typical. abundant hierarchical routing resources based on rout- ing two data nibbles and two control lines per set provide for faster place and route implementations and less rout- ing delay. ttl or cmos input levels programmable per pin for the or3cxx (5.0 v) devices. individually programmable drive capability: 12 ma sink/6 ma source or 6 ma sink/3 ma source. built-in boundary scan ( ieee ? 1149.1 jtag) and ts_all testability function to 3-state all i/o pins. enhanced system clock routing for low skew, high-speed clocks originating on-chip or at any i/o. up to four expressclk inputs allow extremely fast clock- ing of signals on- and off-chip plus access to internal general clock routing. stopclk feature to glitchlessly stop/start expressclks independently by user command. programmable i/o (pio) has: ?fast-capture input latch and input ?p-?p (ff) latch for reduced input setup time and zero hold time. ?capability to (de)multiplex i/o signals. ?fast access to slic for decodes and pa l -like functions. ?output ff and two-signal function generator to reduce clk to output propagation delay. ?fast open-drain dive capability ?capability to register 3-state enable signal. baseline fpga family used in series 3+ fpscs (?ld programmable system chips) which combine fpga logic and standard cell logic on one device. * pa l is a trademark of advanced micro devices, inc. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc. table 1. orca series 3 (3c and 3t) fpgas the system gate counts range from a logic-only gate count to a gate count assuming 30% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates per pfu/slic), including 12 gates per lut/ff pair (eight per pfu), and 12 gates per slic/ff pair (one per pfu). each of the four pios per pic is counted as 16 gates (two ffs, fast-capture latch, output logic, clk drivers, and i/o buffers). pfus used as ram are counted at four gates per bit, with each pfu capable of imple menting a 32 x 4 ram (or 512 gates) per pfu. device system gates luts registers max user ram max user i/os array size process technology or3t20 36k 1152 1872 18k 192 12 x 12 0.3 ?/4 lm or3t30 48k 1568 2436 25k 221 14 x 14 0.3 ?/4 lm or3t55 80k 2592 3780 42k 288 18 x 18 0.3 ?/4 lm or3c/3t80 116k 3872 5412 62k 342 22 x 22 0.3 ?/4 lm or3t125 186k 6272 8400 100k 342 28 x 28 0.3 ?/4 lm select devices have been discontinued. see ordering information section for product status.
table of contents contents page contents page 2 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas features ......................................................................1 system-level features................................................4 description...................................................................5 fpga overview ..........................................................5 plc logic ...................................................................5 description (continued)................................................6 pic logic ....................................................................6 system features ........................................................6 routing .......................................................................6 configuration ..............................................................6 description (continued)................................................7 isplever development system ................................7 architecture .................................................................7 programmable logic cells ..........................................9 programmable function unit ......................................9 look-up table operating modes .............................11 supplemental logic and interconnect cell (slic).....19 plc latches/flip-flops ............................................23 plc routing resources ...........................................25 plc architectural description ...................................32 rogrammable input/output cells................................34 5 v tolerant i/o ........................................................35 pci compliant i/o .....................................................35 inputs ........................................................................36 outputs .....................................................................39 pic routing resources ............................................42 pic architectural description ....................................43 high-level routing resources..................................45 interquad routing .....................................................45 programmable corner cell routing .........................46 pic interquad (mid) routing ....................................47 clock distribution network ........................................48 pfu clock sources ..................................................48 clock distribution in the plc array ..........................49 clock sources to the plc array ...............................50 clocks in the pics ....................................................50 expressclk inputs ...................................................51 selecting clock input pins ........................................51 special function blocks ............................................52 single function blocks .............................................52 boundary scan .........................................................55 microprocessor interface (mpi) .................................62 powerpc system .....................................................63 i960 system ..............................................................64 mpi interface to fpga .............................................65 mpi setup and control .............................................66 programmable clock manager (pcm) ......................70 pcm registers .........................................................71 delay-locked loop (dll) mode ...............................73 phase-locked loop (pll) mode ..............................74 pcm/fpga internal interface ...................................77 pcm operation .........................................................77 pcm detailed programming .................................... 78 pcm applications .................................................... 81 pcm cautions ......................................................... 82 fpga states of operation........................................ 83 initialization .............................................................. 83 configuration ........................................................... 84 start-up ................................................................... 85 reconfiguration ....................................................... 86 partial reconfiguration ............................................ 86 other configuration options .................................... 86 using isplever to generate configuration ram data ....................................... 87 configuration data frame ....................................... 87 bit stream error checking ....................................... 89 fpga configuration modes...................................... 90 master parallel mode ............................................... 90 master serial mode ................................................. 91 asynchronous peripheral mode .............................. 92 microprocessor interface (mpi) mode ..................... 92 slave serial mode ................................................... 95 slave parallel mode ................................................. 95 daisy-chaining ........................................................ 96 daisy-chaining with boundary scan ....................... 97 absolute maximum ratings...................................... 98 recommended operating conditions ..................... 98 electrical characteristics .......................................... 99 timing characteristic description .......................... 101 description ............................................................. 101 pfu timing ........................................................... 102 plc timing ............................................................ 109 slic timing ........................................................... 109 pio timing ............................................................. 110 special function blocks timing ............................. 113 clock timing .......................................................... 121 configuration timing ............................................. 131 readback timing ................................................... 140 input/output buffer measurement conditions ........ 141 output buffer characteristics ................................. 142 or3cxx ................................................................. 142 or3txxx ................................................................ 143 estimating power dissipation ................................. 144 or3cxx ................................................................. 144 or3txxx................................................................. 145 pin information ....................................................... 147 pin descriptions...................................................... 147 package compatibility ........................................... 151 compatibility with or2c/txxa series .................... 152 package thermal characteristics........................... 188 fpga maximum junction temperature ................ 190 package coplanarity .............................................. 191 package parasitics ................................................. 191 package outline diagrams..................................... 192 select devices have been discontinued. see ordering information section for product status.
table of contents contents page contents page lattice semiconductor 3 orca series 3c and 3t fpgas november 2006 data sheet terms and definitions .............................................192 144-pin tqfp .........................................................193 208-pin sqfp ........................................................194 208-pin sqfp2 ......................................................195 240-pin sqfp .........................................................196 240-pin sqfp2 .......................................................197 256-pin pbga ........................................................198 352-pin pbga ........................................................199 432-pin ebga ........................................................200 ordering information................................................201 select devices have been discontinued. see ordering information section for product status.
4 4 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas system-level features system-level features reduce glue logic requirements and make a system on a chip possible. these features in the orca series 3 include: full pci local bus compliance. dual-use microprocessor interface (mpi) can be used for con?uration, readback, device control, and device status, as well as for a general-purpose inter- face to the fpga. glueless interface to i960 * and powerpc ? processors with user-con?urable address space provided. parallel readback of con?uration data capability with the built-in microprocessor interface. programmable clock manager (pcm) adjusts clock phase and duty cycle for input clock rates from 5 mhz to 120 mhz. the pcm may be combined with fpga logic to create complex functions, such as dig- ital phase-locked loops (dpll), frequency counters, and frequency synthesizers or clock doublers. two pcms are provided per device. true, internal, 3-state, bidirectional buses with simple control provided by the slic. 32 x 4 ram per pfu, con?urable as single- or dual- port at >176 mhz. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. * i960 is a registered trademark of intel corporation. ? powerpc is a registered trademark of international business machines corporation. table 2. orca series 3 system performance 1. implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. implemented using two 32 x 12 roms and one 12-bit adder, one 8-bit input, one ?ed operand, one 16-bit output. 3. implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 pfus contain only pipelining registers). 4. implemented using 32 x 4 ram mode with read data on 3-state buffer to bidirectional read/write bus. 5. implemented using 32 x 4 dual-port ram mode. 6. implemented in one partially occupied slic with decoded output set up to ce in same plc. 7. implemented in ?e partially occupied slics. parameter # pfus speed unit -4 -5 -6 -7 16-bit loadable up/down counter 2 78 102 131 168 mhz 16-bit accumulator 2 78 102 131 168 mhz 8 x 8 parallel multiplier: multiplier mode, unpipelined 1 rom mode, unpipelined 2 multiplier mode, pipelined 3 11.5 8 15 19 51 76 25 66 104 30 80 127 38 102 166 mhz mhz mhz 32 x 16 ram (synchronous): single-port, 3-state bus 4 dual-port 5 4 4 97 127 127 166 151 203 192 253 mhz mhz 128 x 8 ram (synchronous): single-port, 3-state bus 4 dual-port 5 8 8 88 88 116 116 139 139 176 176 mhz mhz 8-bit address decode (internal): using softwired luts using slics 6 0.25 0 4.87 2.35 3.66 1.82 2.58 1.23 2.03 0.99 ns ns 32-bit address decode (internal): using softwired luts using slics 7 2 0 16.06 6.91 12.07 5.41 9.01 4.21 7.03 3.37 ns ns 36-bit parity check (internal) 2 16.06 12.07 9.01 7.03 ns select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 5 data sheet november 2006 orca series 3c and 3t fpgas description fpga overview the orca series 3 fpgas are a new generation of sram-based fpgas built on the successful or2c/ txxa fpga series, with enhancements and innova- tions geared toward todays high-speed designs and tomorrows systems on a single chip. designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the orca 2c/2t devices, series 3 more than doubles the logic available in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 3 devices contain many new patented enhancements and are offered in a variety of pack- ages, speed grades, and temperature ranges. the orca series 3 fpgas consist of three basic ele- ments: programmable logic cells (plcs), programma- ble input/output cells (pics), and system-level features. an array of plcs is surrounded by pics. each plc contains a programmable function unit (pfu), a sup- plemental logic and interconnect cell (slic), local rout- ing resources, and con?uration ram. most of the fpga logic is performed in the pfu, but decoders, pa l -like functions, and 3-state buffering can be per- formed in the slic. the pics provide device inputs and outputs and can be used to register signals and to per- form input demultiplexing, output multiplexing, and other functions on two output signals. some of the sys- tem-level functions include the new microprocessor interface ( mpi ) and the programmable clock manager ( pcm ). plc logic each pfu within a plc contains eight 4-input (16-bit) look-up tables (luts), eight latches/?p-?ps (ffs), and one additional ?p-?p that may be used indepen- dently or with arithmetic functions. the pfu is organized in a twin-quad fashion: two sets of four luts and ffs that can be controlled indepen- dently. luts may also be combined for use in arith- metic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be con?ured as a synchronous 32 x 4 sin- gle- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the slic is connected to plc routing resources and to the outputs of the pfu. it contains 3-state, bidirectional buffers and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert (aoi) to perform pa l -like functions. the 3-state drivers in the slic and their direct connections to the pfu out- puts make fast, true 3-state buses possible within the fpga, reducing required routing and allowing for real- world system performance. select devices have been discontinued. see ordering information section for product status.
6 6 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas description (continued) pic logic series 3 pic addresses the demand for ever-increas- ing system clock speeds. each pic contains four pro- grammable inputs/outputs (pios) and routing resources. on the input side, each pio contains a fast- capture latch that is clocked by an expressclk. this latch is followed by a latch/ff that is clocked by a sys- tem clock from the internal general clock routing. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer. two input signals are available to the plc array from each pio, and the orca 2c/2t capability to use any input pin as a clock or other global input is maintained. on the output side of each pio, two outputs from the plc array can be routed to each output ?p-?p, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. the output ff in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the i/o buffer associated with each pad is very similar to the orca 2c/2t series buffer with a new, fast, open-drain option for ease of use on system buses. system features series 3 also provides system-level functionality by means of its dual-use microprocessor interface and its innovative programmable clock manager. these func- tional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in todays high-speed systems. routing the abundant routing resources of the orca series 3 fpgas are organized to route signals individually or as buses with related control signals. clocks are routed on a low-skew, high-speed distribution network and may be sourced from plc logic, externally from any i/o pad, or from the very fast expressclk pins. express- clks may be glitchlessly and independently enabled and disabled with a programmable control signal using the new stopclk feature. the improved pic routing resources are now similar to the patented intra-plc routing resources and provide great ?xibility in moving signals to and from the pios. this ?xibility translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to speci? pins. con?uration the fpgas functionality is determined by internal con?uration ram. the fpgas internal initialization/ con?uration circuitry loads the con?uration data at powerup or under system control. the ram is loaded by using one of several con?uration modes. the con- ?uration data resides externally in an eeprom or any other storage media. serial eeproms provide a sim- ple, low pin count method for con?uring fpgas. a new, easy method for con?uring the devices is through the microprocessor interface. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 7 data sheet november 2006 orca series 3c and 3t fpgas description (continued) isplever development system the isplever development system is used to pro- cess a design from a netlist to a con?ured fpga. this system is used to map a design onto the orca archi- tecture and then place and route it using isplevers timing-driven tools. the development system also includes interfaces to, and libraries for, other popular cae tools for design entry, synthesis, simulation, and timing analysis. the isplever development system interfaces to front-end design entry tools and provides the tools to produce a con?ured fpga. in the design ?w, the user de?es the functionality of the fpga at two points in the design ?w: at design entry and at the bit stream generation stage. following design entry, the development systems map, place, and route tools translate the netlist into a routed fpga. a static timing analysis tool is provided to deter- mine device speed and a back-annotated netlist can be created to allow simulation. timing and simulation out- put ?es from isplever are also compatible with many third-party analysis tools. its bit stream generator is then used to generate the con?uration data which is loaded into the fpgas internal con?uration ram. when using the bit stream generator, the user selects options that affect the functionality of the fpga. com- bined with the front-end tools, isplever produces con?uration data that implements the various logic and routing options discussed in this data sheet. architecture the orca series 3 fpga comprises three basic ele- ments: plcs, pics, and system-level functions. figure 1 shows an array of programmable logic cells (plcs) surrounded by programmable input/output cells (pics). also shown are the interquad routing blocks (hiq, viq) present in series 3. system-level functions (located in the corners of the array) and the routing resources and con?uration ram are not shown in figure 1. the or3t55 array in figure 1 has plcs arranged in an array of 18 rows and 18 columns. the location of a plc is indicated by its row and column so that a plc in the second row and the third column is r2c3. pics are located on all four sides of the fpga between the plcs and the device edge. pics are indicated using pt and pb to designate pics on the top and bottom sides of the array, respectively, and pl and pr to des- ignate pics along the left and right sides of the array, respectively. the position of a pic on an edge of the array is indicated by a number, counting from left to right for pt and pb and top to bottom for pl and pr pics. each pic contains routing resources and four program- mable i/os (pios). each pio contains the necessary i/o buffers to interface to bond pads. pios in series 3 fpgas also contain input and output ffs, fast open- drain capability on output buffers, special output logic functions, and signal multiplexing/demultiplexing capa- bilities. plcs comprise a programmable function unit (pfu), a supplemental logic and interconnect cell (slic), and routing resources. the pfu is the main logic element of the plc, containing elements for both combinatorial and sequential logic. combinatorial logic is done in look-up tables (luts) located in the pfu. the pfu can be used in different modes to meet different logic requirements. the luts twin-quad architecture pro- vides a con?urable medium-/large-grain architecture that can be used to implement from one to eight inde- pendent combinatorial logic functions or a large num- ber of complex logic functions using multiple luts. the ?xibility of the lut to handle wide input functions, as well as multiple smaller input functions, maximizes the gate count per pfu while increasing system speed. the luts can be programmed to operate in one of three modes: combinatorial, ripple, or memory. in com- binatorial mode, the luts can realize any 4- or 5-input logic function and many multilevel logic functions using orca s softwired lut ( swl ) connections. in ripple mode, the high-speed carry logic is used for arithmetic functions, comparator functions, or enhanced data path functions. in memory mode, the luts can be used as a 32 x 4 synchronous read/write or read-only memory, in either single- or dual-port mode. select devices have been discontinued. see ordering information section for product status.
8 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas architecture (continued) 5-4489(f) figure 1. or3t55 array vi pl9 pl8 pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl13 pl12 pl11 pr12 pr11 pr9 pr8 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr13 pr18 pr17 pr16 pr15 pr14 rmid pr10 pt1 pt2 pt3 pt4 pt5 pt6 pt7 pt8 pt9 pt11 pt12 r1c1 r1c2 r1c3 r1c4 r1c5 r1c6 r1c7 r1c8 r1c9 r1c10 r1c18 r1c17 r1c16 r1c15 r1c14 r1c13 r1c12 r1c11 pt13 pt14 pt15 pt16 pt17 pt18 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pb9 pb10 pb11 pb12 pl18 pl17 pl16 pl15 pl14 pb13 pb14 pb15 pb16 pb17 pb18 pl10 bmid pt10 viq r2c1 r2c2 r2c3 r2c4 r2c5 r2c6 r2c7 r2c8 r2c9 r2c10 r3c1 r3c2 r3c3 r3c4 r3c5 r3c6 r3c7 r3c8 r3c9 r3c10 r4c1 r4c2 r4c3 r4c4 r4c5 r4c6 r4c7 r4c8 r4c9 r4c10 r5c1 r5c2 r5c3 r5c4 r5c5 r5c6 r5c7 r5c8 r5c9 r5c10 r6c1 r6c2 r6c3 r6c4 r6c5 r6c6 r6c7 r6c8 r6c9 r6c10 r7c1 r7c2 r7c3 r7c4 r7c5 r7c6 r7c7 r7c8 r7c9 r7c10 r8c1 r8c2 r8c3 r8c4 r8c5 r8c6 r8c7 r8c8 r8c9 r8c10 r9c1 r9c2 r9c3 r9c4 r9c5 r9c6 r9c7 r9c8 r9c9 r9c10 r10c1 r10c2 r10c3 r10c4 r10c5 r10c6 r10c7 r10c8 r10c9 r10c10 r2c18 r2c17 r2c16 r2c15 r2c14 r2c13 r2c12 r2c11 r3c18 r3c17 r13c16 r3c15 r3c14 r3c13 r3c12 r3c11 r4c18 r4c17 r4c16 r4c15 r4c14 r4c13 r4c12 r4c11 r5c18 r5c17 r5c16 r5c15 r5c14 r5c13 r5c12 r5c11 r6c18 r6c17 r6c16 r6c15 r6c14 r6c13 r6c12 r6c11 r7c18 r7c17 r7c16 r7c15 r7c14 r7c13 r7c12 r7c11 r8c18 r8c17 r8c16 r8c15 r8c14 r8c13 r8c12 r8c11 r9c18 r9c17 r9c16 r9c15 r9c14 r9c13 r9c12 r9c11 r10c18 r10c17 r10c16 r10c15 r10c14 r10c13 r10c12 r10c11 r18c18 r18c17 r18c16 r18c15 r18c14 r18c13 r18c12 r18c11 r17c18 r17c17 r17c16 r17c15 r17c14 r17c13 r17c12 r17c11 r16c18 r16c17 r16c16 r16c15 r16c14 r16c13 r16c12 r16c11 r15c18 r15c17 r15c16 r15c15 r15c14 r15c13 r15c12 r15c11 r14c18 r14c17 r14c16 r14c15 r14c14 r14c13 r14c12 r14c11 r13c18 r13c17 r13c16 r13c15 r13c14 r13c13 r13c12 r13c11 r12c18 r12c17 r12c16 r12c15 r12c14 r12c13 r12c12 r12c11 r11c18 r11c17 r11c16 r11c15 r11c14 r11c13 r11c12 r11c11 r18c10 r18c9 r18c8 r18c7 r18c6 r18c5 r18c4 r18c3 r18c2 r18c1 r17c10 r17c9 r17c8 r17c7 r17c6 r17c5 r17c4 r17c3 r17c2 r17c1 r16c10 r16c9 r16c8 r16c7 r16c6 r16c5 r16c4 r16c3 r16c2 r16c1 r15c10 r15c9 r15c8 r15c7 r15c6 r15c5 r15c4 r15c3 r15c2 r15c1 r14c10 r14c9 r14c8 r14c7 r14c6 r14c5 r14c4 r14c3 r14c2 r14c1 r13c10 r13c9 r13c8 r13c7 r13c6 r13c5 r13c4 r13c3 r13c2 r13c1 r12c10 r12c9 r12c8 r12c7 r12c6 r12c5 r12c4 r12c3 r12c2 r12c1 r11c10 r11c9 r11c8 r11c7 r11c6 r11c5 r11c4 r11c3 r11c2 r11c1 hiq tmid lmid select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 9 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells the programmable logic cell (plc) consists of a pro- grammable function unit (pfu), a supplemental logic and interconnect cell (slic), and routing resources. all plcs in the array are functionally identical with only minor differences in routing connectivity for improved routability. the pfu, which contains eight 4-input luts, eight latches/ffs, and one ff for logic implementation, is discussed in the next section, followed by discus- sions of the slic and plc routing resources. programmable function unit the pfus are used for logic. each pfu has 50 external inputs and 18 outputs and can operate in several modes. the functionality of the inputs and outputs depends on the operating mode. the pfu uses 36 data input lines for the luts, eight data input lines for the latches/ffs, ?e control inputs (aswe, clk, ce, lsr, sel), and a carry input (cin) for fast arithmetic functions and general-purpose data input for the ninth ff. there are eight combinatorial data outputs (one from each lut), eight latched/registered outputs (one from each latch/ff), a carry-out (cout), and a registered carry-out (regcout) that comes from the ninth ff. the carry-out signals are used principally for fast arithmetic functions. figure 2 and figure 3 show high-level and detailed views of the ports in the pfu, respectively. the eight sets of lut inputs are labeled as k 0 through k 7 with each of the four inputs to each lut having a suf? of _x, where x is a number from 0 to 3. there are four f5 inputs labeled a through d. these inputs are used for a ?th lut input for 5-input luts or as a selector for multi- plexing two 4-input luts. the eight direct data inputs to the latches/ffs are labeled as din[7:0]. registered lut outputs are shown as q [7:0] , and combinatorial lut outputs are labeled as f [7:0] . the pfu implements combinatorial logic in the luts and sequential logic in the latches/ffs. the luts are static random access memory (sram) and can be used for read/write or read-only memory. each latch/ff can accept data from its associated lut. alternatively, the latches/ffs can accept direct data from din[7:0], eliminating the lut delay if no combina- torial function is needed. additionally, the cin input can be used as a direct data source for the ninth ff. the lut outputs can bypass the latches/ffs, which reduces the delay out of the pfu. it is possible to use the luts and latches/ffs more or less independently, allowing, for instance, a comparator function in the luts simulta- neously with a shift register in the ffs. 5-5752(f) figure 2. pfu ports the pfu can be con?ured to operate in four modes: logic mode, half-logic mode, ripple mode, and memory (ram/rom) mode. in addition, ripple mode has four submodes and ram mode can be used in either a single- or dual-port memory fashion. these submodes of operation are discussed in the following sections. 5-5752(f) f5d k 7 _0 k 7 _1 k 7 _2 k 7 _3 k 6 _0 k 6 _1 k 6 _2 k 6 _3 k 5 _0 k 5 _1 k 5 _2 k 5 _3 k 4 _0 k 4 _1 k 4 _2 k 4 _3 f5c din7 din6 din5 din4 din3 din2 din1 din0 cin f5b k 3 _0 k 3 _1 k 3 _2 k 3 _3 k 2 _0 k 2 _1 k 2 _2 k 2 _3 k 1 _0 k 1 _1 k 1 _2 k 1 _3 k 0 _0 k 0 _1 k 0 _2 k 0 _3 f5a lsr clk ce sel aswe programmable function unit (pfu) q7 q6 q5 q4 q3 q2 q1 q0 cout regcout f7 f6 f5 f4 f3 f2 f1 f0 select devices have been discontinued. see ordering information section for product status.
10 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) 5-5743(f) note: all multiplexers without select inputs are con?uration selector multiplexers. figure 3. simpli?d pfu diagram sel cin d ce ck s/r ff8 regcout cout 1 aswe lsr k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 f5d k7_0 k7_1 k7_2 k5_3 k4_0 k4_1 k4_2 k4_3 f5c clk a b c d a b c d a b c d k4 k5 k6 k7 din7 din6 din5 din4 reg5 d0 d1 ce ck s/r dsel q5 f5 reg6 d0 d1 ce ck s/r dsel q6 f6 reg7 d0 d1 ce ck s/r dsel q7 f7 reg4 d0 d1 ce ck s/r dsel q4 f4 a b c d f5mode45 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 f5b k3_0 k3_1 k3_2 k1_3 k0_0 k0_1 k0_2 k0_3 f5a a b c d a b c d a b c d k0 k1 k2 k3 din3 din2 din1 din0 reg1 d0 d1 ce ck s/r dsel q1 f1 reg2 d0 d1 ce ck s/r dsel q2 f2 reg3 d0 d1 ce ck s/r dsel q3 f3 reg0 d0 d1 ce ck s/r dsel q0 f0 a b c d f5mode01 f5mode67 f5mode23 0 0 0 0 0 0 0 0 0 0 0 0 ce 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 11 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) look-up table operating modes the operating mode affects the functionality of the pfu input and output ports and internal pfu routing. for exam- ple, in some operating modes, the din[7:0] inputs are direct data inputs to the pfu latches/ffs. in memory mode, the same din[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into lut memory. table 3 lists the basic operating modes of the lut. figure 4?igure 10 show block diagrams of the lut operating modes. the accompanying descriptions demonstrate each modes use for generating logic. pfu control inputs each pfu has ?e routable control inputs and an active-low, asynchronous global set/reset (gsrn) signal that affects all latches and ffs in the device. the ?e control inputs are clk, lsr, ce, aswe, and sel, and their functionality for each logic mode of the pfu (discussed subsequently) is shown in table 4. the clock signal to the pfu is clk, ce stands for clock enable, which is its primary function. lsr is the local set/reset signal that can be con?ured as synchronous or asynchronous. the selection of set or reset is made for each latch/ff and is not a function of the signal itself. aswe stands for add/subtract/write enable, which are its functions, along with being an optional clock enable, and sel is used to dynamically select between direct pfu input and lut output data as the input to the latches/ffs. all of the control signals can be disabled and/or inverted via the con?uration logic. a disabled clock enable indi- cates that the clock is always enabled. a disabled lsr indicates that the latch/ff never sets/resets (except from gsrn). a disabled sel input indicates that din[7:0] pfu inputs are routed to the latches/ffs. for logic and ripple modes of the pfu, the lsr, ce, and aswe (as a clock enable) inputs can be disabled individually for each nibble (latch/ff[3:0], latch/ff[7:4]) and for the ninth ff. table 3. look-up table operating modes mode function logic 4- and 5-input luts; softwired luts; latches/ffs with direct input or lut input; cin as direct input to ninth ff or as pass through to cout. half logic/ half rip- ple upper four luts and latches/ffs in logic mode; lower four luts and latches/ffs in ripple mode; cin and ninth ff for logic or ripple functions. ripple all luts combined to perform ripple-through data functions. eight lut registers available for direct-in use or to register ripple output. ninth ff dedicated to ripple out, if used. the submodes of ripple mode are adder/subtractor, counter, multiplier, and comparator. memory all luts and latches/ffs used to create a 32 x 4 synchronous dual-port ram. can be used as single- port or as rom. select devices have been discontinued. see ordering information section for product status.
12 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) table 4. control input functionality mode clk lsr ce aswe sel logic clk to all latches/ ffs lsr to all latches/ ffs, enabled per nib- ble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff select between lut input and direct input for eight latches/ffs half logic/ half ripple clk to all latches/ ffs lsr to all latches/ff, enabled per nibble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff ripple logic control input select between lut input and direct input for eight latches/ffs ripple clk to all latches/ ffs lsr to all latches/ ffs, enabled per nib- ble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff ripple logic control input select between lut input and direct input for eight latches/ffs memory (ram) clk to ram port enable 2 port enable 1 write enable not used memory (rom) optional for sync. outputs not used not used not used not used logic mode the pfu diagram of figure 3 represents the logic mode of operation. in logic mode, the eight luts are used individually or in ?xible groups to implement user logic functions. the latches/ffs may be used in con- junction with the luts or separately with the direct pfu data inputs. there are three basic submodes of lut operation in pfu logic mode: f4 mode, f5 mode, and softwired lut (swl) mode. combinations of these submodes are possible in each pfu. f4 mode, shown simpli?d in figure 4, illustrates the uses of the basic 4-input luts in the pfu. the output of an f4 lut can be passed out of the pfu, captured at the luts associated latch/ff, or multiplexed with the adjacent f4 lut output using one of the f5[a:d] inputs to the pfu. only adjacent lut pairs (k 0 and k 1 , k 2 and k 3 , k 4 and k 5 , k 6 and k 7 ) can be multiplexed, and the output always goes to the even-numbered output of the pair. the f5 submode of the lut operation, shown simpli- ?d in figure 4, indicates the use of 5-input luts to implement logic. 5-input luts are created from two 4-input luts and a multiplexer. the f5 lut is the same as the multiplexing of two f4 luts described previously with the constraint that the inputs to the f4 luts be the same. the f5[a:d] input is then used as the ?th lut input. the equations for the two f4 luts will differ by the assumed value for the f5[a:d] input, one f4 lut assuming that the f5[a:d] input is zero, and the other assuming it is a one. the selection of the appropriate f4 lut output in the f5 mux by the f5[a:d] signal creates a 5-input lut. any combination of f4 and f5 luts is allowed per pfu using the eight 16-bit luts. examples are eight f4 luts, four f5 luts, and a combination of four f4 plus two f5 luts. 5-5970(f) figure 4. simpli?d f4 and f5 logic modes k 7 f7 k 7 f6 k 6 f5d k 6 f6 k 5 f5 k 5 f4 k 4 f5c k 4 f4 k 3 f3 k 3 f2 k 2 f5b k 2 f2 k 1 f1 k 1 f0 k 0 f5a k 0 f0 k 7 /k 6 f6 k 5 /k 4 f4 k 3 /k 2 f2 k 1 /k 0 f0 f5 mode multiplexed f4 mode f4 mode select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 13 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) softwired lut submode uses f4 and f5 luts and internal pfu feedback routing to generate complex logic func- tions up to three lut-levels deep. figure 3 shows multiplexers between the k z [3:0] inputs to the pfu and the luts. these multiplexers can be independently con?ured to route certain lut outputs to the input of other luts. in this manner, very complex logic functions, some of up to 21 inputs, can be implemented in a single pfu at greatly enhanced speeds. figure 5 shows several softwired lut topologies. in this ?ure, each circle represents either an f4 or f5 lut. it is important to note that an lut output that is fed back for softwired use is still available to be registered or output from the pfu. this means, for instance, that a logic equation that is needed by itself and as a term in a larger equa- tion need only be generated once and plc routing resources will not be required to use it in the larger equation. figure 5. softwired lut topology examples 5-5753(f) f4 key: f5 4-input lut 5-input lut 5-5754(f) f4 f4 f4 f4 f4 f4 f4 f4 four 7-input functions in one pfu f5 f5 f5 f5 two 9-input functions in one pfu f5 f5 f5 f5 one 17-input function in one pfu f5 f5 f4 one 21-input function in one pfu f4 f4 f4 f4 f4 f4 f4 two of four 10-input functions in one pfu f4 f4 f4 f4 3 one of two 12-input functions in one pfu select devices have been discontinued. see ordering information section for product status.
14 14 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) half-logic mode series 3 fpgas are based upon a twin-quad architec- ture in the pfus. the byte-wide nature (eight luts, eight latches/ffs) may just as easily be viewed as two nibbles (two sets of four luts, four latches/ffs). the two nibbles of the pfu are organized so that any nib- ble-wide feature (excluding some softwired lut topolo- gies) can be swapped with any other nibble-wide feature in another pfu. this provides for very ?xible use of logic and for extremely ?xible routing. the half- logic mode of the pfu takes advantage of the twin- quad architecture and allows half of a pfu, k [7:4] and associated latches/ffs, to be used in logic mode while the other half of the pfu, k [3:0] and associated latches/ ffs, is used in ripple mode. in half-logic mode, the ninth ff may be used as a general-purpose ff or as a register in the ripple mode carry chain. ripple mode the pfu luts can be combined to do byte-wide ripple functions with high-speed carry logic. each lut has a dedicated carry-out net to route the carry to/from any adjacent lut. using the internal carry circuits, fast arithmetic, counter, and comparison functions can be implemented in one pfu. similarly, each pfu has carry-in (cin, fcin) and carry-out (cout, fcout) ports for fast-carry routing between adjacent pfus. the ripple mode is generally used in operations on two data buses. a single pfu can support an 8-bit ripple function. data buses of 4 bits and less can use the nibble-wide ripple chain that is available in half-logic mode. this nibble-wide ripple chain is also useful for longer ripple chains where the length modulo 8 is four or less. for example, a 12-bit adder (12 modulo 8 = 4) can be implemented in one pfu in ripple mode (8 bits) and one pfu in half-logic mode (4 bits), freeing half of a pfu for general logic mode functions. each lut has two operands and a ripple (generally carry) input, and provides a result and ripple (generally carry) output. a single bit is rippled from the previous lut and is used as input into the current lut. for lut k 0 , the ripple input is from the pfu cin or fcin port. the cin/fcin data can come from either the fast-carry routing (fcin) or the pfu input (cin), or it can be tied to logic 1 or logic 0. in the following discussions, the notations lut k 7 /k 3 and f[7:0]/f[3:0] are used to denote the lut that pro- vides the carry-out and the data outputs for full pfu ripple operation (k 7 , f[7:0]) and half-logic ripple operation (k 3 , f[3:0]), respectively. the ripple mode diagram in figure 6 shows full pfu ripple operation, with half-logic ripple connections shown as dashed lines. the result output and ripple output are calculated by using generate/propagate circuitry. in ripple mode, the two operands are input into k z [1] and k z [0] of each lut. the result bits, one per lut, are f[7:0]/f[3:0] (see figure 6). the ripple output from lut k 7 /k 3 can be routed on dedicated carry circuitry into any of four adja- cent plcs, and it can be placed on the pfu cout/ fcout outputs. this allows the plcs to be cascaded in the ripple mode so that nibble-wide ripple functions can be expanded easily to any length. result outputs and the carry-out may optionally be reg- istered within the pfu. the capability to register the rip- ple results, including the carry output, provides for improved counter performance and simpli?d pipelin- ing in arithmetic functions. figure 6. ripple mode 5-5755(f) f7 k 7 [1] k 7 [0] k 7 d q c c dq q7 regcout cout f6 k 6 [1] k 6 [0] k 6 d q q6 f4 k 4 [1] k 4 [0] k 4 d q q4 f3 k 3 [1] k 3 [0] k 3 d q q3 f2 k 2 [1] k 2 [0] k 2 d q q2 f1 k 1 [1] k 1 [0] k 1 d q q1 f5 k 5 [1] k 5 [0] k 5 d q q5 f0 k 0 [1] k 0 [0] k 0 d q q0 cin/fcin fcout select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 15 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) the ripple mode can be used in one of four submodes. the ?st of these is adder-subtractor submode . in this submode, each lut generates three separate out- puts. one of the three outputs selects whether the carry-in is to be propagated to the carry-out of the cur- rent lut or if the carry-out needs to be generated. if the carry-out needs to be generated, this is provided by the second lut output. the result of this selection is placed on the carry-out signal, which is connected to the next lut carry-in or the cout/fcout signal, if it is the last lut (k 7 /k 3 ). both of these outputs can be any equation created from k z [1] and k z [0], but in this case, they have been set to the propagate and gener- ate functions. the third lut output creates the result bit for each lut output connected to f[7:0]/f[3:0]. if an adder/subtrac- tor is needed, the control signal to select addition or subtraction is input on aswe, with a logic 0 indicating subtraction and a logic 1 indicating addition. the result bit is created in one-half of the lut from a single bit from each input bus k z [1:0], along with the ripple input bit. the second submode is the counter submode (see figure 7). the present count, which may be initialized via the pfu din inputs to the latches/ffs, is supplied to input k z [0], and then output f[7:0]/f[3:0] will either be incremented by one for an up counter or decre- mented by one for a down counter. if an up/down counter is needed, the control signal to select the direc- tion (up or down) is input on aswe with a logic 1 indi- cating an up counter and a logic 0 indicating a down counter. generally, the latches/ffs in the same pfu are used to hold the present count value. figure 7. counter submode 5-5756(f) f7 k 7 [0] k 7 d q c c dq q7 regcout cout f6 k 6 [0] k 6 d q q6 f4 k 4 [0] k 4 d q q4 f3 k 3 [0] k 3 d q q3 f2 k 2 [0] k 2 d q q2 f1 k 1 [0] k 1 d q q1 f5 k 5 [0] k 5 d q q5 f0 k 0 [0] k 0 d q q0 cin/fcin fcout select devices have been discontinued. see ordering information section for product status.
16 16 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) in the third submode, multiplier submode , a single pfu can affect an 8 x 1 bit (4 x 1 for half-ripple mode) multiply and sum with a partial product (see figure 8). the multiplier bit is input at aswe, and the multiplicand bits are input at k z [1], where k 7 [1] is the most signi? cant bit (msb). k z [0] contains the partial product (or other input to be summed) from a previous stage. if aswe is logical 1, the multiplicand is added to the par- tial product. if aswe is logical 0, 0 is added to the par- tial product, which is the same as passing the partial product. cin/fcin can bring the carry-in from the less signi?ant pfus if the multiplicand is wider than 8 bits, and cout/fcout holds any carry-out from the multi- plication, which may then be used as part of the prod- uct or routed to another pfu in multiplier mode for multiplicand width expansion. ripple modes fourth submode features equality comparators. the functions that are explicitly available are a > b, a b, and a < b, where the value for a is input on k z [0], and the value for b is input on k z [1]. a value of 1 on the carry-out signals valid argument. for example, a carry-out equal to 1 in ab submode indi- cates that the value on k z [0] is greater than or equal to the value on k z [1]. conversely, the functions a < b, a + b, and a > b are available using the same functions but with a 0 output expected. for example, a > b with a 0 output indicates a < b. table 5 shows each function and the output expected. if larger than 8 bits, the carry-out signal can be cas- caded using fast-carry logic to the carry-in of any adja- cent pfu. the use of this submode could be shown using figure 6, except that the cin/fcin input for the least signi?ant pfu is controlled via con?uration. key: c = con?uration data. figure 8. multiplier submode table 5. ripple mode equality comparator functions and outputs equality function isplever submode true, if carry-out is: a > ba > b1 a < ba < b1 a ba b1 a < b a > b0 a > b a < b0 a = b a b0 5-5757(f) k 7 [1] k 7 [0] + d q c c dq 1 0 0 k 7 aswe k 4 [1] k 4 [0] + d q 1 0 0 k 4 k 3 [1] k 3 [0] + d q 1 0 0 k 3 k 2 [1] k 2 [0] + d q 1 0 0 k 2 k 1 [1] k 1 [0] + d q 1 0 0 k 1 k 6 [1] k 6 [0] + d q 1 0 0 k 6 k 5 [1] k 5 [0] + d q 1 0 0 k 5 k 0 [1] k 0 [0] + d q 1 0 0 k 0 f7 q7 regcout cout f6 q6 f4 q4 f3 q3 f2 q2 f1 q1 f5 q5 f0 q0 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 17 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) memory mode the series 3 pfu can be used to implement a 32 x 4 (128-bit) synchronous, dual-port random access memory (ram). a block diagram of a pfu in memory mode is shown in figure 9. this ram can also be con?ured to work as a single-port memory and because initial values can be loaded into the ram during con?uration, it can also be used as a read-only memory (rom). figure 9. memory mode the pfu memory mode uses all luts and latches/ffs including the ninth ff in its implementation as shown in figure 9. the read address is input at the k z [3:0] and f5[a:d] inputs where k z [0] is the lsb and f5[a:d] is the msb, and the write address is input on cin (msb) and din[7, 5, 3, 1], with din[1] being the lsb. write data is input on din[6, 4, 2, 0], where din[6] is the msb, and read data is available combinatorially on f[6, 4, 2, 0] and registered on q[6, 4, 2, 0] with f[6] and q[6] being the msb. the write enable signal is input at aswe, and two write port enables are input on ce and lsr. the pfu clk signal is used to synchronously write the data. the polarities of the clock, write enable, and port enables are all programmable. write-port enables may be disabled if they are not to be used. 5-5969(f) q6 q4 q2 q0 d 5 q cin(wa4) k z [3:0] 4 f5[a:d] d q din7(wa3) d q din5(wa2) d q din3(wa1) d q din1(wa0) d q din6(wd3) d q din4(wd2) d q din2(wd1) d q din0(wd0) d q aswe(wren) en s/r ce(wpe1) lsr(wpe2) clk 4 write write read read 4 f6 f4 f2 f0 d q d q d q d q write ram clock address[4:0] address[4:0] data[3:0] data[3:0] enable select devices have been discontinued. see ordering information section for product status.
18 18 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) data is written to the write data, write address, and write enable registers on the active edge of the clock, but data is not written into the ram until the next clock edge one-half cycle later. the read port is actually asynchronous, providing the user with read data very quickly after setting the read address, but timing is also provided so that the read port may be treated as fully synchronous for write then read applications. if the read and write address lines are tied together (main- taining msb to msb, etc.), then the dual-port ram operates as a synchronous single-port ram. if the write enable is disabled, and an initial memory contents is provided at con?uration time, the memory acts as a rom (the write data and write address ports and write port enables are not used). wider memories can be created by operating two or more memory mode pfus in parallel, all with the same address and control signals, but each with a different nibble of data. to increase memory word depth above 32, two or more plcs can be used. figure 10 shows a 128 x 8 dual-port ram that is implemented in eight plcs. this ?ure demonstrates data path width expan- sion by placing two memories in parallel to achieve an 8-bit data path. depth expansion is applied to achieve 128 words deep using the 32-word deep pfu memo- ries. in addition to the pfu in each plc, the slic (described in the next section) in each plc is used for read address decodes and 3-state drivers. the 128 x 8 ram shown could be made to operate as a single-port ram by tying (bit-for-bit) the read and write addresses. to achieve depth expansion, one or two of the write address bits (generally the msbs) are routed to the write port enables as in figure 10. for 2 bits, the bits select which 32-word bank of ram of the four available from a decode of two wpe inputs is to be written. simi- larly, 2 bits of the read address are decoded in the slic and are used to control the 3-state buffers through which the read data passes. the write data bus is common, with separate nibbles for width expansion, across all plcs, and the read data bus is common (again, with separate nibbles) to all plcs at the output of the 3-state buffers. figure 10 also shows a new optional capability to pro- vide a read enable for rams/roms in series 3 using the slic cell. the read enable will 3-state the read data bus when inactive, allowing the write data and read data buses to be tied together if desired. figure 10. memory mode expansion example?28 x 8 ram 5-5749(f) rd[7:0] we wa[6:0] ra[6:0] clk wa ra wpe0 wpe1 we wd[7:4] 5 5 4 plc 8 wd[7:0] 8 7 7 wa ra wpe0 wpe1 we rd[3:0] wd[3:0] 5 5 4 plc rd[7:4] wa ra wpe0 wpe1 we wd[7:4] 5 5 4 plc wa ra wpe0 wpe1 we rd[3:0] wd[3:0] 5 5 4 plc rd[7:4] re 4 4 4 4 pfu pfu pfu pfu slic slic slic slic select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 19 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) supplemental logic and interconnect cell (slic) each plc contains a supplemental logic and intercon- nect cell (slic) embedded within the plc routing, out- side of the pfu. as its name indicates, the slic performs both logic and interconnect (routing) func- tions. its main features are 3-statable, bidirectional buffers, and a pa l -like decoder capability. figure 11 shows a diagram of a slic with all of its features shown. all modes of the slic are not available at one time. each slic contains ten bidirectional (bidi) buffers, each buffer capable of driving left and/or right out of the slic. these bidi buffers are twin-quad in nature and are segregated into two groups of four (nibbles) and a third group of two for control. each of these groups of bidis can drive from the left (bli[9:0]) to the right (bro[9:0]), the right (bri[9:0]) to the left (blo[9:0]), or from the central input (i[9:0]) to the left and/or right. this central input comes directly from the pfu outputs (o[9:0]). each of the bidis in the nibble-wide groups also has a 3-state buffer capability, but not the third group. there is one 3-state control (tri) for each slic, with the capability to invert or disable the 3-state control for each group of four bidis. separate 3-state control for each nibble-wide group is achievable by using the slics decoder (dec) output, driven by the group of two bidis, to control the 3-state of one bidi nibble while using the tri signal to control the 3-state of the other bidi nibble. figure 12 and figure 13 show the slic in buffer mode with available 3-state control from the tri and dec signals. if the entire slic is acting in a buffer capacity, the dec output may be used to gen- erate a constant logic 1 (vhi) or logic 0 (vlo) signal for general use. the slic may also be used to generate pa l -like and- or with optional invert (aoi) functions or a decoder of up to 10 bits. each group of buffers can feed into an and gate (4-input and for the nibble groups and 2- input and for the other two buffers). these and gates then feed into a 3-input gate that can be con?ured as either an and gate or an or gate. the output of the 3- input gate is invertible and is output at the dec output of the slic. figure 16 shows the slic in full decoder mode. the functionality of the slic is parsed by the two nibble-wide groups and the 2-bit buffer group. each of these groups may operate independently as bidi buff- ers (with or without 3-state capability for the nibble- wide groups) or as a pa l /decoder. as discussed in the memory mode section, if the slic is placed into one of the modes where it contains both buffers and a decode or aoi function (e.g., buf_buf_dec mode), the dec output can be gated with the 3-state input signal. this allows up to a 6-input decode (e.g., buf_dec_dec mode) plus the 3-state input to control the enable/disable of up to four buffers per slic. figure 12?igure 16 show several con?u- rations of the slic, while table 6 shows all of the pos- sible modes. table 6. slic modes mode # mode buf [3:0] buf [7:4] buf [9:8] 1 buffer buffer buffer buffer 2 buf_buf_dec buffer buffer decoder 3 buf_dec_buf buffer decoder buffer 4 buf_dec_dec buffer decoder decoder 5 dec_buf_buf decoder buffer buffer 6 dec_buf_dec decoder buffer decoder 7 dec_dec_buf decoder decoder buffer 8 decoder decoder decoder decoder select devices have been discontinued. see ordering information section for product status.
20 20 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) figure 11. slic all modes diagram figure 12. buffer mode 5-5744(f) bri9 i9 bli9 bri8 i8 bli8 bri7 i7 bli7 bri6 i6 bli6 bri5 i5 bli5 bri4 i4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl09 br09 bl08 br08 bl07 br07 bl06 br06 bl05 br05 bl04 br04 bl03 br03 bl02 br02 bl01 br01 bl00 br00 dec dec 0/1 0/1 tri 0/1 0/1 high z when low 5-5745(f) bri9 i9 bli9 bri8 i8 bli8 bri7 i7 bli7 bri6 i6 bli6 bri5 i5 bli5 bri4 i4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl09 br09 bl08 br08 bl07 br07 bl06 br06 bl05 br05 bl04 br04 bl03 br03 bl02 br02 bl01 br01 bl00 br00 tri 0/1 0/1 1 0 dec this can be used a vhi or vlo high z when low to generate select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 21 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) figure 13. buffer-buffer-decoder mode figure 14. buffer-decoder-buffer mode 5-5746(f) bri9 bli9 bri8 bli8 bri7 i7 bli7 bri6 i6 bli6 bri5 i5 bli5 bri4 i4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl07 br07 bl06 br06 bl05 br05 bl04 br04 bl03 br03 bl02 br02 bl01 br01 bl00 br00 tri dec 1 1 1 1 high z when low high z when low 5-5747(f) bri7 bli7 bri6 bli6 bri5 bli5 bri4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl03 br03 bl02 br02 bl01 br01 bl00 br00 tri dec bri9 i9 bli9 bri8 i8 bli8 bl09 br09 bl08 br08 1 1 high z when low select devices have been discontinued. see ordering information section for product status.
22 22 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) figure 15. buffer-decoder-decoder mode figure 16. decoder mode 5-5750(f) bri7 bli7 bri6 bli6 bri5 bli5 bri4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl03 br03 bl02 br02 bl01 br01 bl00 br00 tri dec bri9 bli9 bri8 bli8 1 1 high z when low 5-5748(f) bri7 bli7 bri6 bli6 bri5 bli5 bri4 bli4 bri3 bli3 bri2 bli2 bri1 bli1 bri0 bli0 dec bri9 bli9 bri8 bli8 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 23 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) plc latches/flip-flops the eight general-purpose latches/ffs in the pfu can be used in a variety of con?urations. in some cases, the con?uration options apply to all eight latches/ffs in the pfu and some apply to the latches/ffs on a nib- ble-wide basis where the ninth ff is considered inde- pendently. for other options, each latch/ff is independently programmable. in addition, the ninth ff can be used for a variety of functions. table 7 summarizes these latch/ff options. the latches/ffs can be con?ured as either positive- or negative-level sensitive latches, or positive or negative edge-triggered ?p-?ps (the ninth register can only be ff). all latches/ffs in a given pfu share the same clock, and the clock to these latches/ffs can be inverted. the input into each latch/ff is from either the corresponding lut output (f[7:0]) or the direct data input (din[7:0]). the latch/ff input can also be tied to logic 1 or to logic 0, which is the default. * not available for ff[8]. the eight latches/ffs in a pfu share the clock (clk) and options for clock enable (ce), local set/reset (lsr), and front-end data select (sel) inputs. when ce is dis- abled, each latch/ff retains its previous value when clocked. the clock enable, lsr, and sel inputs can be inverted to be active-low. the set/reset operation of the latch/ff is controlled by two parameters: reset mode and set/reset value. when the global set/reset ( gsrn ) and local set/reset (lsr) signals are not asserted, the latch/ff operates normally. the reset mode is used to select a synchronous or asynchronous lsr operation. if synchronous, lsr has the option to be enabled only if clock enable (ce or aswe) is active or for lsr to have priority over the clock enable input, thereby setting/resetting the ff inde- pendent of the state of the clock enable. the clock enable is supported on ffs, not latches. it is imple- mented by using a 2-input multiplexer on the ff input, with one input being the previous state of the ff and the other input being the new data applied to the ff. the select of this 2-input multiplexer is clock enable (ce or aswe), which selects either the new data or the previ- ous state. when the clock enable is inactive, the ff out- put does not change when the clock edge arrives. table 7. con?uration ram controlled latch/ flip-flop operation function options common to all latches/ffs in pfu lsr operation asynchronous or synchronous clock polarity noninverted or inverted front-end select* direct (din[7:0]) or from lut (f[7:0]) lsr priority either lsr or ce has priority latch/ff mode latch or ?p-?p enable gsrn gsrn enabled or has no effect on pfu latches/ffs set individually in each latch/ff in pfu set/reset mode set or reset by group (latch/ff[3:0], latch/ff[7:4], and ff[8]) clock enable ce or aswe or none lsr control lsr or none select devices have been discontinued. see ordering information section for product status.
24 24 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) the gsrn signal is only asynchronous, and it sets/ resets all latches/ffs in the fpga based upon the set/ reset con?uration bit for each latch/ff. the set/reset value determines whether gsrn and lsr are set or reset inputs. the set/reset value is independent for each latch/ff. a new option is available to disable the gsrn function per pfu after initial device con?ura- tion. the latch/ff can be con?ured to have a data front- end select. two data inputs are possible in the front- end select mode, with the sel signal used to select which data input is used. the data input into each latch/ff is from the output of its associated lut, f[7:0], or direct from din[7:0], bypassing the lut. in the front- end data select mode, both signals are available to the latches/ffs. if either or both of these inputs is unused or is unavail- able, the latch/ff data input can be tied to a logic 0 or logic 1 instead (the default is logic 0). the latches/ffs can be con?ured in three basic modes: 1. local synchronous set/reset: the input into the pfus lsr port is used to synchronously set or reset each latch/ff. 2. local asynchronous set/reset: the input into lsr asynchronously sets or resets each latch/ff. 3. latch/ff with front-end select, lsr either synchro- nous or asynchronous: the data select signal selects the input into the latches/ffs between the lut output and direct data in. for all three modes, each latch/ff can be indepen- dently programmed as either set or reset. figure 17 provides the logic functionality of the front-end select, global set/reset, and local set/reset operations. the ninth pfu ff, which is generally associated with registering the carry-out signal in ripple mode func- tions, can be used as a general-purpose ff. it is only an ff and is not capable of being con?ured as a latch. because the ninth ff is not associated with an lut, there is no front-end data select. the data input to the ninth ff is limited to the cin input, logic 1, logic 0, or the carry-out in ripple and half-logic modes. key: c = con?uration data. figure 17. latch/ff set/reset configurations din logic 0 logic 1 f ce d s_set s_reset clk set reset q lsr gsrn cd ce/aswe d clk set reset lsr cd ce ce/aswe d clk set reset cd ce ce/aswe din sel gsrn din logic 0 logic 1 f din logic 0 logic 1 f lsr gsrn q q select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 25 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) plc routing resources generally, the isplever development system is used to automatically route interconnections. interactive routing with the isplever design editor (epic) is also available for design optimization. to use epic for inter- active layout, an understanding of the routing resources is needed and is provided in this section. the routing resources consist of switching circuitry and metal interconnect segments. generally, the metal lines which carry the signals are designated as routing segments. the switching circuitry connects the routing segments, providing one or more of three basic func- tions: signal switching, ampli?ation, and isolation. a net running from a pfu or pic output (source) to a plc or pic input (destination) consists of one or more routing segments, connected by switching circuitry called con?urable interconnect points (cips). the following sections discuss plc, pic, and interquad routing resources. this section discusses the plc switching circuitry, intra-plc routing, inter-plc routing, and clock distribution. configurable interconnect points the process of connecting routing segments uses three basic types of switching circuits: two types of con- ?urable interconnect points (cips) and bidirectional buffers (bidis). the basic element in cips is one or more pass transistors, each controlled by a con?ura- tion ram bit. the two types of cips are the mutually exclusive (or multiplexed) cip and the independent cip. a mutually exclusive set of cips contains two or more cips, only one of which can be on at a time. an inde- pendent cip has no such restrictions and can be on independent of the state of other cips. figure 18 shows an example of both types of cips. key: c = con?uration data. 5-5973(c) figure 18. configurable interconnect point 3-statable bidirectional buffers bidirectional buffers, previously described in the slic section of the programmable logic cell discussion, pro- vide isolation as well as ampli?ation for signals routed a long distance. bidirectional buffers are also used to route signals diagonally in the plc (described later in the subsection entitled intra-plc routing), and bidis can be used to indirectly route signals through the switching routing (xsw) segments. any number from zero to ten bidis can be used in a given plc. multiplexed cip a b c o a b c o cd independent cip a b cd b a = 2 select devices have been discontinued. see ordering information section for product status.
26 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) general routing structure routing resources in series 3 fpgas generally consist of routing segments in groups of ten, with varying lengths and connectivity to logic and other routing resources. the varying lengths of routing segments provides a hierarchy of routing capability from chip-length routes to routes within a plc. the hierarchical nature of the routing provides the isplever development tools with the necessary resources to route a design completely and to optimize the routing for system speed while reducing the overall power required by the device. within each group of ten routing segments there is an equivalency of connectivity between pairs of segments. these pairs are segments: [0, 4] and [1, 5] and [2, 6] and [3, 7] and [8, 9]. the equivalency in connectivity ensures that signals on either segment in a pair have the same capability to get to a given destination. this, in turn, allows for signal distribution from a source to varying destinations without using special routing. it also provides for routing ?xibility by ensuring that one segment position will not become so congested as to preclude routing a bus or group of signals and allows easy connectivity from either of the twin quads in a source pfu to either of the twin quads in any destination pfu. having ten segments in a group is signi?ant in that it provides for routing a byte of data and two control signals or parity. due to the equivalent pairs of segments, this can also be viewed as routing two nibbles each with a control signal. figure 19 is an overview of the routing for a single plc. 5-5766(f) figure 19. single plc view of inter-plc route segments 2 of 5 line-by-line fins pfu output slic switching sur[9:0] bl[9:0] vxl[9:0] vx5[9:0] vx1l[9:0] sul[9:0] vx1r[9:0] fc lck vck vxh[9:0] bl[9:0] hxh[9:0] hx1u[9:0] hck fc sll[9:0] hx1b[9:0] hx5[9:0] hxl[9:0] br[9:0] sul[9:0] bl[9:0] fc sul[9:0] br[9:0] lck sll[9:0] fc slr[9:0] 5 2 5 2 5 2 key: configurable signal line breaks select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 27 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) intra-plc routing the function of the intra-plc routing resources is to connect the pfus input and output ports to the routing resources used for entry to and exit from the plc. this routing provides pfu feedback, corner turning, or switching from one type of routing resource to another. flexible input structure ( fins ) the ?xible input switching structure ( fins ) in each plc of the orca series 3 provides for the ?xibility of a crossbar switch from the routing resources to the pfu inputs while taking advantage of the routability of shared inputs. connectivity between the plc routing resources and the pfu inputs is provided in two stages. the primary fins switch has 50 inputs that connect the plc routing to the 35 inputs on the sec- ondary switch. the outputs of the second switch con- nect to the 50 pfu inputs. the switches are implemented to provide connectivity for bused signals and individual connections. pfu output switching the pfu outputs are switched onto plc routing resources via the pfu output multiplexer (omux). the pfu output switching segments from the output multi- plexer provide ten connections to the plc routing out of 18 possible pfu outputs (f[7:0], q[7:0], dout, regcout). these output switching segments connect segment for segment to the sur, sul, slr, and sll switching segments described below (e.g., o4 con- nects only to sur4, not sur5). the output switching segments also feed directly into the slic on a seg- ment-by-segment basis. this connectivity is also described below. switching routing segments (xsw) there are four sets of switching routing segments in each plc. each set consists of ten switching elements: sul[9:0], sur[9:0], sll[9:0], and slr[9:0], tradition- ally labeled for the upper-left, upper-right, lower-left, and lower-right sections of the pfus, respectively. the xsw routing segments connect to the pfu inputs and outputs as well as the bidi routing segments, to be described later. they also connect to both the horizon- tal and vertical x1 and x5 routing segments (inter-plc routing resources, described later) in their speci? cor- ner. xsw segments can be used for fast connections between adjacent plcs or pics without requiring the use of inter-plc routing resources. this capability not only increases signal speed on adjacent plc routing, but also reduces routing congestion on the principal inter-plc routing resources. the sll and sur seg- ments combine to provide connectivity to the plcs to the left and right of the current plc; the slr and sul segments combine to provide connectivity to the plcs above and below the current plc. fast routes on switching segments to diagonally adja- cent plcs/pics are possible using the bidi routing segments (discussed below) and the sll and slr switching segments. the br bidi routing segments combine with the sul switching segments of the plc below and to the right of the current plc to connect to that plc. the bl bidi routing segments combine with the sll switching segments of the plc above and to the right of the current plc to connect to that plc. these fast diagonal connections provide a great amount of ?xibility in routing congested areas of logic and in shifting data on a per-plc basis such as per- forming implicit multiplications/divisions in routing between functional logic elements. switching routing segments are also the chief means by which signals are transferred between the inter-plc routing resources and the pfu. each set of switching segments has connectivity to the x1 routing segments, and there is varying connectivity to the x5, xh, and xl inter-plc routing segments. detailed information on switching segment/inter-plc routing connectivity is provided later in this section in the inter-plc routing resources subsection. select devices have been discontinued. see ordering information section for product status.
28 28 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) bidi routing and slic connectivity the slic is connected to the rest of the plc by the bidirectional (bidi) routing segments and the pfu out- put switching segments coming from the pfu output multiplexer. the bidi routing segments (xbid) are labeled as bl for bidi-left and br for bidi-right. each set of br and bl xbid segments is composed of ten bidirectional lines (note that these lines are diagramed as ten input lines to the slic and ten output lines from the slic that can be used in a mutually exclusive fash- ion). because the slic is connected directly to the out- puts of the pfu, it provides great ?xibility in routing via the xbid segments. the pfu routing segments, o[9:0], only connect to their respective line in the sll, sul, sur, and slr switching segment groups. that is, o9 only connects to sll9, sul9, sur9, and slr9. the bidi lines provide the capability to connect to the other member of the routing set. that means, for example, that o9 can be routed to br8 or bl8. this connectivity can be used as a means to distribute or gather signals on intra-plc routing without disturbing inter-plc resources. as described in the switching routing seg- ments subsection, the bidi routing segments are also used for routes to a diagonally adjacent pfu. in addition to the intra-plc connections, the xbid and output switching segments also have connectivity to the x1, x5, and xl inter-plc routing resources, provid- ing an alternate routing path rather than using plc xsw segments. these connections also provide a path to the 3-state buffers in the slic without encumbering the xsw segments. in this manner, buffering or 3-state control can be added to inter-plc routing without dis- turbing local functionality within a pfu. control signal and fast-carry routing pfu control signal and the fast-carry routing are per- formed using the fins structure and several dedicated routing paths. the fast-carry (fc) routing resources consist of a dedicated bidirectional segment between each orthogonal pair of plcs. this means that a fast- carry can go to or come from each plc to the right or left, above or below the subject plc. the fins struc- ture is used to control the switching of these fast-carry paths between the fast-carry input (fcin) and fast- carry output (fcout) ports of the pfu. the pfu control inputs (ce, sel, lsr, aswe) and cin can be reached via the fins by two special routing segments, e1 and e2. the e1 routing segment pro- vides connectivity between all of the xbid routing seg- ments and the fins . it is unidirectional from the bidi routing to the fins . e1 also provides connectivity to the pfu clock input via fins for a local clock signal. the e2 segment connects the slic dec output to the fins and to a group of cips that provide bidirectional con- nectivity with all of the bidi routing segments. this allows the dec signal to be used in the pfu and/or routed on the bidi segments. it also allows signals to be routed to the pfu on the xbid segments if the slic dec output is not used. there is also a dedicated routing segment from the fins to the slic tri input used for bidi buffer 3-state control. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 29 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) inter-plc routing resources the inter-plc routing is used to route signals between plcs. the routing segments occur in groups of ten, and differ in the numbers of plcs spanned. the x1 routing segments span one plc, the x5 routing seg- ments span ?e plcs, the xh routing segments span one-half the width (height) of the plc array, and the xl routing segments span the width (height) of the plc array. all types of routing segments run in both horizon- tal and vertical directions. table 8 shows the groups of inter-plc routing seg- ments in each plc. in the table, there are two rows/col- umns for x1 lines. they are differentiated by a t for top, b for bottom, l for left, and r for right. in the isplever design editor representation, the horizontal x1 routing segments are located above and below the pfu. the two groups of vertical segments are located on the left side of the pfu. the xl and x5 routing segments only run below and to the left of the pfu, while the xh seg- ments only run above and to the right of the pfu. the indexes specify individual routing segments within a group. for example, the vx5[2] segment runs vertically to the left of the pfu, spans ?e plcs, and is the third line in the 10-bit wide group. plcs are arranged like tiles on the orca device. breaks in routing occur at the middle of the tile (e.g., x1 lines break in the middle of each plc) and run across tiles until the next break. figure 20 provides a global view of inter-plc routing resources across multiple plcs. x1 routing segments. there are a total of 40 x1 rout- ing segments per plc: 20 vertical and 20 horizontal. each of these are subdivided into two, 10-bit wide buses: hx1t[9:0], hx1b[9:0], vx1l[9:0], and vx1r[9:0]. an x1 segment is one plc long. if a signal net is longer than one plc, an x1 segment can be lengthened to n times its length by turning on n ?1 cips. a signal is routed onto an x1 route segment via the switching rout- ing segments or bidi routing segments which also allows the x1 route segment to be connected to other inter-plc segments of different lengths. corner turning between x1 segments is provided through direct con- nections, xsw segments, and xbid segments. x5 routing segments. there are two sets of ten x5 routing segments per plc. one set (vx5[9:0]) runs ver- tically, and the other (hx5[9:0]) runs horizontally. each x5 segment traverses ?e plcs before it is broken by a cip. two x5 segments in each group break in each plc. the two that break are in an equivalent pair; for example, x5[0] and x5[4]. the x5 segments that break shift by one at the next plc. for example, if hx5[0] and hx5[4] are broken at the current plc, hx5[1] and hx5[5] will be broken at the plc to the right of the current plc. there are direct connections to the bidi routing segments in the plc at which the x5 segments break, on both sides of the break. signal corner turning is enabled by cips in each plc that allow the broken x5 segments to directly connect to the broken x5 seg- ments that run in the orthogonal direction. x5 corner turning can also be accomplished via the xsw and xbid segments in a plc. in addition, the x5 segments are connected to the fins and pfu outputs on a bit- by-bit basis by the xsw segments. x5 segments can be connected for signal runs in multiples of ?e plcs, or they can be combined with x1 and xh routing segments for runs of varying distances. table 8. inter-plc routing resources horizontal routing segments vertical routing segments distance spanned hx1u[9:0] vx1r[9:0] one plc hx1b[9:0] vx1l[9:0] one plc hx5[9:0] vx5[9:0] five plcs hx5[9:0] vx5[9:0] five plcs hxl[9:0] vxl[9:0] plc array hxh[9:0] vxh[9:0] 1/2 plc array hclk vclk plc array select devices have been discontinued. see ordering information section for product status.
30 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) 5-5767(f) figure 20. multiple plc view of inter-plc routing pfu pfu pfu pfu pfu pfu pfu pfu pfu hxh[9:0] hx1[9:0] hclk hx1[9:0] hx5[9:0] hxl[9:0] hxh[9:0] hx1[9:0] hclk hx1[9:0] hx5[9:0] hxl[9:0] hx1[9:0] hx5[9:0] hxl[9:0] hxh[9:0] hx1[9:0] hclk vx1l[9:0] vx5[9:0] vclk vxh[9:0] vx1[9:0] vxl[9:0] vx5[9:0] vclk vxh[9:0] vxl[9:0] vx5[9:0] vx1[9:0] vclk vxh[9:0] vx1[9:0] vx1[9:0] vx1[9:0] vx1[9:0] 10 2 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 slic slic slic slic slic slic slic slic slic plc boundary 2 of 10 line-by-line 10 2 key: configurable signal-line breaks: select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 31 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) xl routing lines. the xl routing lines run vertically and horizontally the height and width of the array, respectively. there are a total of 20 xl routing lines per plc: ten horizontal (hxl[9:0]) and ten vertical (vxl[9:0]). each of the xl lines connects to the pic routing at either end. the xl lines are intended prima- rily for global signals that must travel long distances and require minimum delay and/or skew, such as clocks or 3-state buses. each xl line (also called a long line) drives a buffer in each plc that can drive onto the horizontal and verti- cal local clock routing segments (lclk) in the plc. also, two out of each group of ten xl segments in each plc can be driven by a buffer attached to a clock spine (described later) allowing local distribution of global clock signals. more general-purpose connections to the long lines can be made through the xbid segments in a plc. each long line is connected to an xbid segment on a bit-by-bit basis. these bidi connections allow cor- ner turning from horizontal to vertical long lines, and connection between long lines and x1 or x5 segments. xh routing segments . ten by-half (xh) routing seg- ments run horizontally (hxh[9:0]) and ten xh routing segments run vertically (vxh[9:0]) in each row and col- umn in the array. these routing segments travel a dis- tance of one-half the plc array before being broken in the middle of the array in the interquad area (discussed later). they also connect at the periphery of the fpga to the pics, like the xl lines. xh routing segments con- nect to the plcs only by switching segments. they are intended for fast signal interconnect. clock (and global ce and lsr) routing segments. for a very fast and low-skew clock (or other global sig- nal tree), clock routing segments run the entire height and width of the plc array. there are two clock routing segments per plc: one horizontal (hclk) and one ver- tical (vclk). the source for these clock routing seg- ments can be any of the i/o buffers in the pic, the series 3 expressclk inputs, user logic, or the pro- grammable clock manager ( pcm ). the horizontal clock routing segments (hclk) are alternately driven by the left and right pics. the vertical clock routing segments (vclk) are alternately driven by the top and bottom pics. the clock routing segments are designed to be a clock spine. in each plc, there is a fast connection available from the clock segment to a long-line driver (described earlier). with this connection, one of the clock routing segments in each plc can be used to drive one of the ten xl routing segments perpendicular to it, which, in turn, creates a clock spine tree. this feature is dis- cussed in detail in the clock distribution network sec- tion. special connectivity is provided in each plc to connect the clock enable signals (ce and aswe) and the lsr signal to the clock network for fast global control signal distribution. ce and aswe have a special connection to the horizontal clock spine, and lsr has a special connection to the vertical clock spine. this allows both signals to be routed globally within the same plc, if desired; however, this will consume some of the resources available for clock signal routing. if using these spines, the clock enable signal must come from the right or left edge of the device, and the lsr signal must come from the top or bottom of the device due to their horizontal and vertical connectivity, respectively, to the clock network. minimizing routing delay the cip is an active element used to connect two rout- ing segments. as an active element, it adds signi? cantly to the resistance and capacitance of a routing network (net), thus increasing the nets delay. the advantage of the x1 segment over an x5 segment is routing ?xibility. a net from one plc to the next is eas- ily routed by using x1 routing segments. as more cips are added to a net, the delay increases. to increase speed, routes that are greater than two plcs away are routed on the x5 routing segments because a cip is located only in every ?th plc. a net that spans eight plcs requires seven x1 routing segments and six cips. using x5 routing segments, the same net uses two routing segments and one cip. select devices have been discontinued. see ordering information section for product status.
32 32 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) plc architectural description figure 21 is an architectural drawing of the plc (as seen in isplever) that re?cts the pfu, the routing segments, and the cips. a discussion of each of the letters in the drawing follows. a . these are switching routing segments (xsw) that give the router ?xibility. in general switching theory, the more levels of indirection there are in the routing, the more routable the network is. the xsw seg- ments can also connect to the xsw lines in adjacent plcs. b . these cips connect the x1 routing. these are located in the middle of the plc to allow the block to connect to either the left end of the horizontal x1 segment from the right or the right end of the hori- zontal x1 segment from the left, or both. by symme- try, the same principle is used in the vertical direction. c . this set of cips is used to connect the x1 and x5 nets to the xsw segments or to other x1 and x5 nets. the cips on the major diagonal allow data to be transmitted on a bit-by-bit basis from x1 nets to the xsw segments and between the x1 and x5 nets. d . this structure is the supplemental logic and inter- connect cell, or slic. it contains 3-statable bidirec- tional buffers and logic for building decoders and and-or-invert type structures. e . these are the primary and secondary elements of the ?xible input structure or fins . fins is a switch matrix that provides high connectivity while retaining routing capability. fins also includes feedback paths for softwired lut implementation. f . this is the pfu output switch matrix. it is a complex switch network which, like the fins at the input, pro- vides high connectivity and maintains routability. g . this set of cips allows an xbid segment to transfer a signal to/from xsw segments on each side. the bidis can access the pfu through the xsw seg- ments. these cips allow data to be routed through the bidis for ampli?ation or 3-state control and con- tinue to another plc. they also provide an alterna- tive routing resource to improve routability. h . these cips are used to transfer data from/to the xbid segments to/from the x1 and xl routing seg- ments. these cips have been optimized to allow the bidi buffers to drive the loads usually seen when using each type of routing segment. i. clock input to pfu. j . these are the ten switched output routing segments from the pfu. they connect to the plc switching segments and are input to the slic. k . these lines deliver the auxiliary signals clock enable (ce), local set/reset (lsr), front-end select (sel), add/subtract/write enable (aswe), as well as the carry signals (cin and fcin) to the latches/ffs. l . this is the local clock buffer. any of the horizontal and vertical xl lines can drive the clock input of the plc latches/ffs. the clock routing segments (vclk and hclk) and multiplexers/drivers are used to con- nect to the xl routing segments for low-skew, low- delay global signals. m . these routing segments are used to route the fast- carry signal to/from the neighboring four plcs. the carry-out (cout) and registered carry-out (reg- cout) can also be routed out of the pfu. n . this is the e2 control routing segment. it runs from the slic dec output to the fins and also provides connectivity to all xbid segments. o . the xh routing segments run one-half the length (width) of the array before being broken by a cip. p . these cips connect the xh segments to the xsw segments. q . the xbid segments are used to connect the slic to the xsw segments, x1 segments, x5 segments, and xl lines, as well as providing for diagonal plc to plc connections. r . these cips provide connections from the xbid seg- ments to the e1/e2 routing segments that feed pfu control inputs ce, lsr, cin, aswe, sel, and the clock input. alternatively, these cips connect the bidi lines to the decoder (dec) output of the slic, for routing the dec signal. s . these are clock spines (vclk and hclk) with the multiplexers and drivers to connect to the xl routing segments. t . these cips connect xbid segments to switching segments in diagonally and orthogonally adjacent pfus. u . these cips connect xsw segments to the pfu out- put segments. v . these cips connect xsw segments in orthogonally adjacent pfus. w .this is the slic 3-state control routing segment from the fins to the slic 3-state control. x. this is the e1 control routing segment. it provides a pfu input path from all xbid segments. y. these cips are used to select which xbid segments are connected to the e1/e2 signal as described in (r). select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 33 data sheet november 2006 orca series 3c and 3t fpgas programmable logic cells (continued) 5-5758(f) figure 21. plc architecture h s m g r l h h d r slic output switching pfu primary fins secondary fins b w y a b p m o q m o f pv k j u u u x a b h b g c h q q t m s q q l h t e e n q c c c a c c c a a a a c a a c c c c a select devices have been discontinued. see ordering information section for product status.
34 34 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells the programmable input/output cells (pics) are located along the perimeter of the device. the pics name is represented by a two-letter designation to indi- cate on which side of the device it is located followed by a number to indicate in which row or column it is located. the ?st letter, p, designates that the cell is a pic and not a plc. the second letter indicates the side of the array where the pic is located. the four sides are left (l), right (r), top (t), and bottom (b). the indi- vidual i/o pad is indicated by a single letter (either a, b, c, or d) placed at the end of the pic name. as an example, pl10a indicates a pad located on the left side of the array in the tenth row. each pic interfaces to four bond pads and contains the necessary routing resources to provide an interface between i/o pads and the plcs. each pic is com- posed of four programmable i/os (pios) and signi?ant routing resources. each pio contains input buffers, output buffers, routing resources, latches/ffs, and logic and can be con?ured as an input, output, or bidirectional i/o. pics in the series 3 fpgas have signi?ant local rout- ing resources, similar to routing in the plcs. this new routing increases the ability to ? user pinouts prior to placement and routing of a design and still maintain routability. the ?xibility provided by the routing also provides for increased signal speed due to a greater variety of signal paths possible. included in the pic routing is a fast path from the input pins to the slics in each of the three adjacent plcs (one orthogonal and two diagonal). this feature allows for input signals to be very quickly processed by the slic decoder function and used on-chip or sent back off of the fpga. also new to the series 3 pios are latches and ffs and options for using fast, dedicated clocks called expressclks. these features will all be discussed in subsequent sections. a diagram of a single pio (one of four in a pic) is shown in figure 22. table 9 provides an overview of the programmable functions in an i/o cell. 5-5805(f).c figure 22. or3c/txxx programmable input/output (pio) image from isplever in2 in1 d0 d1 ck sp sd lsr inregmode latchff latch ff d ck normal inverted reset set level mode ttl cmos up down none pull-mode buffer ts fast slew sink reset set lsr sp ck d out1 out2 eclk sclk ce ce_over_lsr lsr_over_ce async lsr enable_gsr disable_gsr out1outreg out2outreg out1out2 nor xor xnor and nand or pio logic clkin 0 0 1 0 pad q q 1 pd to routing q 1 eclk sclk pmux from routing mode lsr ck d0 q select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 35 data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells (continued) 5 v tolerant i/o the i/o on the or3txxx series devices allow intercon- nection to both 3.3 v and 5 v devices (selectable on a per-pin basis). the or3txxx devices will drive the pin to the 3.3 v lev- els when the output buffer is enabled. if the other device being driven by the or3txxx device has ttl- compatible inputs, then the device will not dissipate much input buffer power. this is because the or3txxx output is being driven to a higher level than the ttl level required. if the other device has a cmos-compat- ible input, the amount of input buffer power will also be small. both of these power values are dependent upon the input buffer characteristics of the other device when driven at the or3txxx output buffer voltage levels. the or3txxx device has internal programmable pull- ups on the i/o buffers. these pull-up voltages are always referenced to v dd and are always suf?ient to pull the input buffer of the or3txxx device to a high state. the pin on the or3txxx device will be at a level 1.0 v below v dd (minimum of 2.0 v with a minimum v dd of 3.0 v). this voltage is suf?ient to pull the exter- nal pin up to a 3.3 v cmos high input level (1.8 v, min) or a ttl high input level (2.0 v, min) in a 5 v tolerant system. therefore, in a 5 v tolerant system using 5 v cmos parts, care must be taken to evaluate the use of these pull-ups to pull the pin of the or3txxx device to a typical 5 v cmos high input level (2.2 v, min). pci compliant i/o the i/o on the or3txxx series devices allows compli- ance with pci local bus (rev. 2.2) 5 v and 3.3 v sig- naling environments. the signaling environment used for each input buffer can be selected on a per-pin basis. the selection provides the appropriate i/o clamping diodes for pci compliance. choosing an ibt input buffer will provide pci compliance in or3txxx devices. or3cxx devices have pci local bus compli- ant i/os for 5 v signaling. table 9. pio options input option input level ttl, or3cxx only cmos, or3cxx or or3txxx 3.3 v pci compliant, or3txxx 5 v pci compliant, or3txxx input speed fast, delayed float value pull-up, pull-down, none register mode latch, ff, fast zero hold ff, none (direct input) clock sense inverted, noninverted input selection input 1, input 2, clock input output option output drive current 12 ma/6 ma or 6 ma/3 ma output function normal, fast open drain output speed fast, slewlim, sinklim output source ff direct-out, general routing output sense active-high, active-low 3-state sense active-high, active-low (3-state) ff clocking expressclk , system clock clock sense inverted, noninverted logic options see table 10. i/o controls option clock enable active-high, active-low, always enabled set/reset level active-high, active-low, no local reset set/reset type synchronous, asynchronous set/reset priority ce over lsr, lsr over ce gsr control enable gsr, disable gsr select devices have been discontinued. see ordering information section for product status.
36 36 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells (continued) inputs as outlined earlier in table 9, there are six major options on the pio inputs that can be selected in the isplever tools. for or3cxx devices, the inputs and bidirectional buffers can be con?ured as either ttl or cmos compatible. or3txxx devices support cmos levels only for input or bidirectional buffers, have 5 v tolerant i/os as previously explained, but can optionally be selected on a pin-by-pin basis to be pci bus 3.3 v signaling compliant (pci bus 5 v signaling compliance occurs in 5 v tolerant operation). the default buffer upon powerup for the unused sites is 5 v tolerant/5 v pci compliant. consult the orca macro library, series 3 i/o cells, for the appropriate buffers. inputs may have a pull-up or pull-down resistor selected on an input for signal stabilization and power management. input sig- nals in a pio can be passed to pic routing on any of three paths, two general signal paths into pic routing, and/or a fast route into the clock routing system. there is also a programmable delay available on the input. when enabled, this delay affects the in1 and in2 signals of each pio, but not the clock input. the delay allows any signal to have a guaranteed zero hold time when input. this feature is discussed subsequently. inputs should have transition times of less than 500 ns and should not be left ?ating. if any pin is not used, it is 3-stated with an internal pull-up resistor enabled automatically after con?uration. warning : during con?uration, all or3txxx inputs have internal pull-ups enabled. if these inputs are driven to 5 v, they will draw substantial current ( ? 5 ma). this is due to the fact that the inputs are pulled up to 3 v. floating inputs increase power consumption, produce oscillations, and increase system noise. the or3cxx inputs have a typical hysteresis of approximately 280 mv (200 mv for the or3txxx) to reduce sensitivity to input noise. the pic contains input circuitry which pro- vides protection against latch-up and electrostatic dis- charge. the other features of the pio inputs relate to the new latch/ff structure in the input path. as shown in figure 23, the input is optionally passed to a register or latch/register pair. these structures can operate in the modes listed in table 9. in latch mode, the input signal is fed to a latch that is clocked by a system clock signal. the clock may be inverted or noninverted from its sense in the pic routing. there is also a local set/reset signal to the latch from the pic routing. the senses of these signals are also programmable as well as the capability to enable or disable the global set/reset sig- nal and select the set/reset priority. the same control signals may also be used to control the input latch/ff when it is con?ured as a ff instead of a latch, with the addition of another control signal used as a clock enable. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 37 data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells (continued) zero-hold input there are two options for zero-hold input capture in the pio. if input delay mode is selected to delay the signal from the input pin, data can be either registered or latched with guaranteed zero-hold time in the pio using a system clock. to guarantee zero hold, the system clock spine structure must be used for clocking, as will be discussed later. the fast zero-hold mode of the pio input takes advantage of the latch/ff combination and sources the input ff data from a dedicated latch that is clocked by the expressclk from the pic. the expressclk is a clock from a dedi- cated input pin designed for fast, low-skew operation at the i/os and is described more fully in the clock distribu- tion network and pic interquad (mid) routing sections that follow. the combination of expressclk latch and system clock ff guarantees a zero-hold capture of input data in the pio ff, while at the same time reducing input setup time. figure 23 shows a schematic of the fast-capture latch/ff and a sample timing diagram. 5-5974(f) note: ce and lsr signals not shown. figure 23. fast-capture latch and timing d q input data latch clk o i expressclk o i system clk cd = 1 clock enable local set/reset dq ff s/r ce data out to pic routing expressclk system clk input data q latch q ff b acde b acde abcd select devices have been discontinued. see ordering information section for product status.
38 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells (continued) input demultiplexing the combination of input register capability and the two inputs, in1 and in2, from each pio to the internal routing provides for input signal demultiplexing without any additional resources. figure 24 shows the input con?uration and general timing for demultiplexing a multiplexed address and data signal. the pio input signal is sent to both the input latch and directly to in2. the signal is latched on the falling edge of the clock and output to routing at in1. the address and data are then both available at the rising edge of the system clock. these signals may be regis- tered or otherwise processed in the plcs at that clock edge. figure 24 also shows the possible use of the slic decoder to perform an address decode to enable which registers are to receive the input data. although the timing shown is for using the input register as a latch, it may also be used in the same way as an ff. also note that the signals found in pio inputs in1 and in2 can be interchanged. 5-5798(f) figure 24. pio input demultiplexing dec dq pad pio dq ce slic other address lines sclk in1 in2 sclk pio latch plc ff addr1 addr2 addr3 addr4 addr5 data1 data2 data3 data4 data1 data2 data3 addr2 addr3 addr4 addr5 data0 data4 output output pio input plc select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 39 data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells (continued) outputs the pics output drivers have programmable drive capability and slew rates. three propagation delays (fast, slewlim, sinklim) are available on output drivers. the sinklim mode has the longest propagation delay and is used to minimize system noise and minimize power consumption. the fast and slewlim modes allow critical timing to be met. the drive current is 12 ma sink/6 ma source for the slewlim and fast output speed selections and 6 ma sink/3 ma source for the sinklim output. two adja- cent outputs can be interconnected to increase the out- put sink/source current to 24 ma/12 ma. all outputs that are not speed critical should be con?- ured as sinklim to minimize power and noise. the num- ber of outputs that switch simultaneously in the same direction should be limited to minimize ground bounce. to minimize ground bounce problems, locate heavily loaded output buffers near the ground pads. ground bounce is generally a function of the driving circuits, traces on the printed-circuit board, and loads and is best determined with a circuit simulation. at powerup, the output drivers are in slewlim mode, and the input buffers are con?ured as ttl-level com- patible (cmos for or3txxx) with a pull-up. if an output is not to be driven in the selected con?uration mode, it is 3-stated. the output buffer signal can be inverted, and the 3-state control signal can be made active-high, active- low, or always enabled. in addition, this 3-state signal can be registered or nonregistered. additionally, there is a fast, open-drain output option that directly connects the output signal to the 3-state control, allowing the out- put buffer to either drive to a logic 0 or 3-state, but never to drive to a logic 1. because there is no explicit route required to create the open-drain output, its response is very fast. like the input side of the pio, there are two output connections from pic routing to the output side of the pio, out1, and out2. these connections provide for ?xible routing and can be used in data manipulation in the pio as described in subsequent paragraphs. an ff has been added to the output path of the pio. the register has a local set/reset and clock enable. the lsr has the option to be synchronous or asynchro- nous and have priority set as clock enable over lsr or lsr over clock enable. clocking to the output ff can come from either the system clock or the expressclk associated with the pic. the input to the ff can come from either out1 or out2, or it can be tied to v dd or gnd. additionally, the input to the ff can be inverted. output multiplexing the series 3 pio output ff can be combined with the new pio logic block to perform output data multiplexing with no plc resources required. the pio logic block has three multiplexing modes: out1outreg, out2outreg, and out1out2. out1outreg and out2outreg are equivalent except that either out1 or out2 is muxed with the ff, where the ff data is output on the clock phase after the active edge. the simplest multiplexing mode is out1out2. in this mode, the signal at out1 is output to the pad while the clock is low, and the signal on out2 is output to the pad when the clock is high. figure 25 shows a simple schematic of a pio in out1out2 mode and a general timing diagram for multiplexing an address and data signal. often an address will be used to generate or read a data sample from memory with the goal of multiplexing the data onto a single line. in this case, the address often precedes the data by one clock cycle. out1outreg and out2outreg modes of the pio logic can be used to address this situation. because out1outreg mode is equivalent to out2outreg, only out2outreg mode is described here. figure 26 shows a simple pio sche- matic in out2outreg mode and general timing for multiplexing data with a leading address. the address signal on out1 is registered in the pio ff. this delays the address so that it aligns with the data signal. the pio logic block then sends the outreg signal (address) to the pad when the clock is high and the out2 signal (data) to the pad when the clock is low, resulting in an aligned, multiplexed signal. select devices have been discontinued. see ordering information section for product status.
40 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells (continued) note: pio logic mode, out1out2 5-5799(f) figure 25. output multiplexing (out1out2 mode) note: pio logic mode, out1out2 5-5797(f) figure 26. output multiplexing (out2outreg mode) clk addr1 addr2 addr3 addr4 addr5 data2 data3 data4 data5 addr1 addr2 addr3 data1 data2 data3 data4 data1 addr4 out1 out2 pic output plc address pad pio logic out1 out2 clk from routing data from routing pic plc dq clk pad p/o logic out1 out2 pic data clk reg address data addr1 addr2 addr3 addr4 data1 data2 data3 data4 data1 data2 addr1 addr2 addr3 addr4 data3 pad addr addr1 addr2 addr3 addr4 addr5 from routing address from routing select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 41 data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells (continued) pio logic function generator the pio logic block can also generate logic functions based on the signals on the out2 and clk ports of the pio. the functions are and, nand, or, nor, xor, and xnor. table 10 is provided as a summary of the pio logic options. pio register control signals as discussed in the inputs and outputs subsections, the pio latches/ffs have various clock, clock enable (ce), local set/reset (lsr), and global set/reset (gsrn) controls. table 11 provides a summary of these control signals and their effect on the pio latches/ffs. note that all control signals are optionally invertible. table 10. pio logic options option description out1outreg data at out1 output when clock low, data at ff out when clock high. out2outreg data at out2 output when clock low, data at ff out when clock high. out1out2 data at out1 output when clock low, data at out2 when clock high. and output logical and of signals on out2 and clock. nand output logical nand of signals on out2 and clock. or output logical or of signals on out2 and clock. nor output logical nor of signals on out2 and clock. xor output logical xor of signals on out2 and clock. xnor output logical xnor of signals on out2 and clock. table 11. pio register control signals control signal effect/functionality expressclk clocks input fast-capture latch; optionally clocks output ff, or 3-state ff. system clock (sclk) clocks input latch/ff; optionally clocks output ff, or 3-state ff. clock enable (ce) optionally enables/disables input ff (not available for input latch mode); optionally enables/dis- ables output ff; separate ce inversion capability for input and output. local set/reset (lsr) option to disable; affects input latch/ff, output ff, and 3-state ff if enabled. global set/reset (gsrn) option to enable or disable per pio after initial con?uration. set/reset mode the input latch/ff, output ff, and 3-state ff are individually set or reset by both the lsr and gsrn inputs. select devices have been discontinued. see ordering information section for product status.
42 42 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells (continued) pic routing resources the pic routing borrows many of the concepts and constructs from the plc routing. it is designed to be able to gather an 8-bit bidirectional bus from any eight consecutive i/o pads and route them to either or both of the two adjacent plcs. the eight i/o bits do not need to start at a pic boundary; that is, they may start at one of the middle two pios in a pic and span three pics. substantial routing has been added to the pic to off- load plc routing from being used to move signals around the plc array perimeter. this saves plc rout- ing for logic purposes and provides greater ?xibility for locking design pinouts prior to ?al placement and rout- ing of the device, or allowing a change in the pinout late in the design cycle. the pic routing has also been increased substantially to allow routing to the complex pio cells that now allow multiple inputs and outputs per device pin, along with new sequential control signals, such as clock enable, lsr, and clock. pics are grouped in pairs for purposes of discussing pic routing. on the sides of a device, the pics in a pair are referred to as top and bottom. on the top or bottom of a device, the pics in a pair are referred to as left or right. for example, on the top edge of the device, the leftmost pic, pt1, is the left pic of a pair, and pic pt2 is the right pic of that pair. the next pic to the right, pt3, is the left pic of the next pair, and so on. the need for pic pairs stems from the routing of switching segments and plc half- and long-line driv- ers. as described below, the connectivity for these types of routing is grouped across pairs of pics to pro- vide complete and fast routing of i/o signals between a given pic and the three adjacent plcs: one orthogo- nal and two diagonal. pic routing segments use the same terminology as plc routing segments, but are pre?ed with a p to dis- tinguish them as belonging to the pics. pic switching segments. each pic has two groups of switching segments (psw), each group having eight lines with connectivity to the pios in groups of four. one set of switching segments connects to the pic to the left (above), and the other set connects to the switching segments of the pic to the right (below). this means of connectivity between pics using staggered connections of groups of switching segments allows a given pic to route signals to both adjacent pics and all adjacent plcs ef?iently. this provides single signal routing ?xibility and routing of multiple buses on groups of i/os without tying up global routing resources. px1 routing segments. there are ?e px1 routing segments in each pic that run parallel to the edge of the chip on which the pic resides, each broken by a cip in each pic. the px1 segments have connectivity to the psw segments and to the x1 routing segments of the two adjacent plcs. px2 routing segments. there are ?e px2 routing segments in each pic that run parallel to the edge of the chip on which the pic resides. to provide greater routing ?xibility, the cips that break the px2 segments every two pics are staggered across the two pics in a pair. one pic of the pair has break cips on the even- numbered px2 segments, and the other has them on the odd-numbered px2 segments. the px2 segments have connectivity to the psw segments and to the x1 routing segments of the two adjacent plcs. px5 routing segments. there are ten px5 routing segments in each pic that run parallel to the edge of the chip on which the pic resides. two of the ten seg- ments are broken in each pic so that each segment is broken every ?e pics. all ten px5 segments break at the corners of the chip, allowing independent px5 rout- ing on each edge of the chip. the px5 routing seg- ments connect to the psw segments and the x5 and xh routing segments of the two adjacent plcs. pxh routing segments. each pic contains eight pxh routing segments that run parallel to the edge of the chip on which the pic resides. the pxh segments have connectivity with the xl, xh, and one set of xbid rout- ing segments in the immediately adjacent plc. pxl routing segments. there are ten pxl routing segments in each pic that run parallel to the edge of the chip on which the pic resides. each of the xl lines makes a connection to an xl line from the adjacent plc. pic long lines (xl) can be used for global signal distribution just as plc xl lines can. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 43 data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells (continued) pic architectural description the pic architecture as seen in isplever is shown in figure 27. the ?ure is the left pic of a pic pair on the top edge of a series 3 array. both pics in a pair are similar, with the differences mainly lying in the connec- tions between the pic switching segments (psw), the in2 connections across pic boundaries, and the sys- tem clock spine driver residing in only one pic of a pair. a . this is a programmable input/output (pio). there are four pios per pic. the pios contain the pic logic and i/o buffers. b . this is the pic output switching block. it connects the pic switching segments and local clock lines to the pio output and control signals. c . this is the system clock spine switching block and buffer. there is only one system clock spine per pair of pics. its inputs can come from the pic switching segments or any of the eight pio inputs in a pic pair. d . pic switching segments (psw). these routing seg- ments are used to interconnect routing resources within the pic and to a lesser degree, between pics. e . px1 routing segments. the pic x1 routing segments traverse one pic and break at a cip in the middle of each pic. f . px2 routing segments. the pics have routing that traverses two pics between breaks. the breaks are staggered among the ?e px2 segments. g . px5 routing segments. each of the ten pic x5 rout- ing segments traverses ?e pics in between breaks at a cip. two px5 segments break in each pic. h . pxh routing segments. the eight pic xh routing segments traverse half of the array and break at cips in the interquad routing region that is in the middle of the array. i . (not used intentionally for clarity.) j . pxl routing segments. the pic long lines run the entire length of the side of the array. k . x5 routing segments from the adjacent plc routing. l . xl routing segments from the adjacent plc routing. m . x1 routing segments from the adjacent plc routing. n . switching segments from the adjacent plc routing. o . xh routing segments from the adjacent plc routing. p . bidi routing segments from the adjacent plc rout- ing. q . these are the in2 routing segments. there is one in2 line from each pio, and all eight in2 lines from each pic pair are present in both pics of a pair. r . these cips connect the in1 and in2 routing seg- ments from the pios to the pic switching seg- ments. s . these cips break the pic switching segments at the interface between a pic pair. t . these cips connect adjacent plc routing resources to the pic switching segments. u . these cips connect inter-pic routing with the pic switching segments. v . these cips break the px1, px2, and px5 routing at the middle of a pic. the px2 and px5 cip place- ment varies depending on the plc. w . these mutually exclusive buffers can drive one long line signal onto a pic local clock routing segment. x . these mutually exclusive buffers can select a source from one of the local system clock routes to drive the pio 3-state control signal. y . these are the four local system clock routing seg- ments. two come from connections within the pic, one from the other pic in the pair, and one from the adjacent plc. z . these mutually exclusive buffers allow a signal on the pic switching segments to be routed to a sys- tem clock spine or to a pio system clock. aa. expressclk routing line. ab . system clock spine. ac . these various groups of cips connect routing resources from the adjacent plc to the inter-pic routing resources. ad . these buffers provide connectivity between the plc xl (xh) lines and the pic xl (xh) lines or connectivity between one of the in2 routing seg- ments and the pic and/or plc xl (xh) routing segments. ae . these mutually exclusive buffers and cips provide connectivity to the plc xl and xh lines from one of the in2 input segments. af . these buffers allow the in2 signals to drive onto the bidi routing of the adjacent plc, or the bidi routing of the adjacent plc, and the pic switching segments and/or pic half lines may be connected. select devices have been discontinued. see ordering information section for product status.
44 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable input/output cells (continued) 5-5823(f) figure 27. pic architecture aa aa aa b y d d d d e f h j z x ac g ae ad t w r t v u u ac j q q r r c p o n m ad m k l k s af w t h ae ac ab select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 45 data sheet november 2006 orca series 3c and 3t fpgas high-level routing resources the high-level routing resources in the orca series 3 devices are interquad routing, corner cell routing, and pic interquad routing. these resources and their related structures are discussed in the following subsections. interquad routing in the orca series 3 devices, the plc array is split into four equal quadrants. in between these quadrants, routing has been added to route signals between the quadrants and distribute clocks. in addition to general routing, there are four specialized clock routing spines. the general routing is discussed below, followed by the special clock rout- ing. one of the main purposes of interquad routing is to distribute internally generated signals, such as clocks and con- trol signals. there are two types of interquad blocks: vertical and horizontal. vertical interquad blocks (viq) run between quadrants on the left and right, while horizontal interquad blocks (hiq) run between top and bottom quad- rants. interquad lines begin and end in the mid cells that are discussed later. since hiq and viq blocks have the same logic, only the hiq block is described below. the interquad routing connects to x5 and xh segments. it does not affect other local routing (xsw, x1, fast carry), so local routing is the same, whether plc-plc connections cross quadrants or not. figure 28 presents a (not to scale) view of interquad routing. 5-4538(f) figure 28. interquad routing tmid bmid 5555 viq2[4:0] viq4[4:0] viq6[4:0] viq8[4:0] viq0[4:0] viq3[4:0] viq5[4:0] viq7[4:0] viq9[4:0] viq1[4:0] 5 5555 5 lmid rmid hiq7[4:0] hiq5[4:0] hiq3[4:0] hiq1[4:0] hiq9[4:0] hiq6[4:0] hiq4[4:0] hiq2[4:0] hiq0[4:0] hiq8[4:0] 5 5 5 5 5 5 5 5 5 5 fast clock r fast clock l fast clock t fast clock b select devices have been discontinued. see ordering information section for product status.
46 46 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas high-level routing resources (continued) figure 29 shows the connections from the interquad routing to the inter-plc routing for a block of the hori- zontal interquad. the vertical interquad has similar connections. the connections shown in figure 29 are made with plcs located above and below the routing shown in the ?ure. the interquad routing segments, pre?ed ih for interquad horizontal, are in ten groups of ?e lines. any one line from each group can be routed to one of the xh segments from the top of the device (left for vertical interquad), one of the xh segments from the bottom of the device (right for vertical inter- quad), and one of the x5 segments crossing the inter- quad. figure 28 shows four fast middle clock (fast clock) sig- nals with the suf?es t (top), b (bottom), r (right), and l (left), respectively. figure 29 also shows the fast clock r and fast clock l lines; these are dedicated interquad clock spines. they originate in the clkcn- trl special function blocks in the middle of each edge of the device, with the name referencing the edge of origin. for example, fast clock r originates in the clkcntrl block on the right edge of a device. fast clock spines traverse the entire plc array but do not connect to the pics on the edge of the device opposite to the source. each fast clock line connects to two of the xl lines in each plc that run orthogonally to the fast clock. these connections allow the fast clock lines to generate a clock tree that can reach any plc in the device. fast clocks and other clock resources are dis- cussed in the clock distribution network section. programmable corner cell routing programmable routing the programmable corner cell (pcc) contains the cir- cuitry to connect the routing of the two pics in each corner of the device. the pic px1 and px2 segments and eight pic switching segments are directly con- nected together from one pic to another. the px5 lines are all broken with cips and the pic pxl and pxh segments are connected from one block to another through programmable buffers. corner cell special functions in addition to routing functions, special-purpose func- tions are located in each fpga corner. the upper-left pcc contains connections to the boundary-scan logic and microprocessor interface. the upper-right pcc contains connections to the readback logic, connectiv- ity to the global 3-state signal (ts_all), and a pro- grammable clock manager. the lower-left pcc contains connections to the internal oscillator and a programmable clock manager. the lower-right pcc contains connections to the start-up and global reset logic. these functions are all more completely described in the special function blocks section of this data sheet. 5-5821(f) figure 29. hiq block detail ih0[4:0] ih1[4:0] ih2[4:0] ih3[4:0] ih4[4:0] fast clock r ih5[4:0] ih6[4:0] ih7[4:0] ih8[4:0] ih9[4:0] fast clock l bl[9:0] vxl[9:0] vx5[9:0] vx1[9:0] sul[9:0] vx1[9:0] vxh[9:0] bl[9:0] fast vck carry select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 47 data sheet november 2006 orca series 3c and 3t fpgas high-level routing resources (continued) pic interquad (mid) routing there is also connectivity between the pics in each quadrant, as well as a clock control (clkcntrl) mod- ule (discussed in the special function blocks section) between the pic routing and the interquad routing. these blocks are called lmid (left), tmid (top), rmid (right), and bmid (bottom). the tmid routing is shown in figure 30. as with the hiq and viq blocks, the only connectivity to the pic routing is to the global pxh and px5 segments. the pxh segments from the one quadrant can be con- nected through a cip to its counterpart in the opposite quadrant, providing a path that spans the array of pics. since a passive cip is used to connect the two pxh segments, a 3-state signal can be routed on the two pxh segments in the opposite quadrants, and then connected through this cip. as with the hiq and viq blocks, cips and buffers allow nibble-wide connections between the interquad segments, the xh segments, and the x5 segments. 5-5822(f) figure 30. top (tmid) routing expressclk right pic local clocks pic local clocks pxl[9:0] pxh[7:0] px5[9:0] px1[4:0] psw[7:4] psw[3:0] psw[7:4] psw[3:0] px2[4:0] 1v9xl[4] 1v8xl[3] iv7xl[2] fast clock iv7xl[0] iv6xl[3] iv6xl[1] iv5xl[2] iv5xl[0] iv4xl[3] iv3xl[3] iv3xl[1] iv2xl[2] iv2xl[0] iv1xl[3] iv1xl[1] 1v0xl[2] 1v0xl[0] iv4xl1] in2[a:d] from left in[a:d] from right corner expressclk from right from left expressclk left shutoff select devices have been discontinued. see ordering information section for product status.
48 48 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas clock distribution network the series 3 fpgas provide three types of high- speed, low-skew clock distributions: system clock, fast middle clock (fast clock), and expressclk . because of the great variety of sources and distribution for clock signals in the orca series 3, the clock mechanisms will be described here from the inside out. the clock connections to the pfu will be described, followed by clock distribution to the plc array, clock sources to the plc array, and ?ally ending with clock sources and distribution in the pics. the expressclk inputs are new, dedicated clock inputs in series 3 fpgas. they are mentioned in several of the clock network descrip- tions and are described fully later in this section. pfu clock sources within a plc there are ?e sources for the clock signal of the latches/ffs in the pfu. two of the signals are generated off of the long lines (xl) within the plc: one from the set of vertical long lines and one from the set of horizontal long lines. for each of these signals, any one of the ten long lines of each set, vertical or horizon- tal, can generate the clock signal. two of the ?e pfu clock sources come from neighboring plcs. one clock is generated from the plc to the left or right of the cur- rent plc, and one is generated from the plc above or below the current plc. the selection decision as to where these signals come from, above/below and left/ right, is based on the position of the plc in the array and has to do with the alternating nature of the source of the system clock spines (discussed later). the last of the ?e clock sources is also generated within the plc. the e1 control signal, described in the plc routing resources section, can drive the pfu clock. the e1 signal can come from any xbid routing resource in the plc. the selection and switching of clock signals in a plc is performed in the fins . figure 31 shows the pfu clock sources for a set of four adjacent plcs. global control signals the four clock signals in each plc that are generated from the long lines (xl) in the current plc or an adja- cent plc can also be used to drive the pfu clock enable (ce), local set/reset (lsr) and add/subtract/ write enable (aswe) signals. the clock signals gener- ated from vertical long lines can drive ce and aswe, and the clocks generated from horizontal long lines can drive lsr. this allows for low-skew global distribution of two of these three control signals with the clock rout- ing while still allowing a global clock route to occur. 5-6054(f) figure 31. pfu clock sources pfu plc pfu plc pfu plc pfu plc e1 e1 e1 e1 hxl[9:0] hxl[9:0] vxl[9:0] vxl[9:0] select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 49 data sheet november 2006 orca series 3c and 3t fpgas clock distribution network (continued) clock distribution in the plc array system clock (sclk) the clock distribution network, or clock spine network, within the plc array is designed to minimize clock skew while maximizing clock ?xibility. clock ?xibility is expressed in two ways: the ease with which a single clock is routed to the entire array, and the capability to provide multiple clocks to the plc array. there is one horizontal and one vertical clock spine passing through each plc. the horizontal clock spine is sourced from the pic in the same row on either the left- or right-hand side of the array, with the source side (left or right) alternating for each row. the vertical clock spines are similarly sourced from the pics alternating from the top or bottom of a column. each clock spine is capable of driving one of the ten xl routing segments that run orthogonal to it within each plc. full connec- tivity to all pfus is maintained due to the connectivity from the xl lines to the pfu clock signals described in the previous section; however, only an xl line in every other row (column) needs to be driven to allow the given clock signal to be distributed to every pfu. figure 32 is a high-level diagram of the series 3 system clock spine network with sample xl line connections for a 4 x 4 array of plcs. the clock spine structure previously described pro- vides for complete distribution of a clock from any i/o pin to the entire plc array by means of a single clock spine and long lines (xl). this distribution system also provides a means to have many different clocks routed to many different and dispersed locations in the plc array. each spine can carry a different clock signal, so for the or3t55 (which has an 18 x 18 array of plcs, implying nine clock spines per side), 36 input clock sig- nals can be supported using the system clock network. fast clock fast clocks are high-speed, low-skew clock spines that originate from the clkcntrl special function blocks (described later). there are four fast clock spines?ne originating on the middle of each edge of the array. the spines run in the interquad region of the plc array from their source side of the device to the last row or column on the opposite side of the device. the fast clocks connect to two long lines, xl[8] and xl[9], that run orthogonal to the spine direction in each plc. these long lines can then be connected to the pfu clock input in the same manner as the general system clocks, and, like the system clock connections, xl lines are only needed in every other row (column) to distrib- ute a clock to every pfu. the limited number of long- line connections and the low skew of the clkcntrl source combine to make the fast clocks a very robust, low-skew clock source. 5-5801(f).a figure 32. orca series 3 system clock distribution overview (xl) horizontal (xl) unused (xl) (xl) unused sclk spine (xl) unused sclk spine vertical sclk spine sclk spine sclk spine unused sclk spine unused sclk spine unused sclk spine unused sclk spine unused sclk spine select devices have been discontinued. see ordering information section for product status.
50 50 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas clock distribution network (continued) clock sources to the plc array the source of a clock that is globally available to the plc array can be from any user i/o pad, any of the expressclk pads, or an internally generated source. system clock as described in the programmable input/output cells section, pics are grouped in adjacent pairs. any one of the eight pads in a pic pair can drive a clock spine in a row or column. for pic pairs on the top of the chip, the column associated with the left pic has the clock spine, for pairs on the bottom, the right pic column has the spine. the top pic of the pair sources the spine from the left side of the array, and the bottom pic of the pair sources the spine from the right side of the array. clock delay and skew are minimized by having a single clock buffer per pair of pics. the clock spine for each pair can also be driven by one of the four pic switching segments (psw) in each pic of the pair. this allows a signal generated in the plc array to be routed onto the global clock spine network. the system clock output of the programmable clock manager ( pcm ) may also be routed to the global system clock spines via the psw segments. figure 33 shows the clock spine multiplex- ing structure for a pair of pics on the top of the array. fast clock the fast clock spines are sourced to the plc array from each side of the device by the expressclk pads via the clkcntrl function block (described in the special function blocks section). the expressclk and fast clock source from the pads is shown in figure 34 and will be described further in the expressclk inputs subsection. 5-5800(f) figure 33. pic system clock spine generation clocks in the pics because the series 3 fpgas have latches and ffs in the i/os, it is necessary to have clock signal distribution to the pios as well as in the plc array. the system clock, the fast clock, and the expressclk are available for pio clocking. pic system clock there are ?e local system clock lines in each pic. much like the sources for a clock in the pfu, two of the local pic clocks are generated within the pic from long lines. one is generated from the set of ten pic long lines (pxl) that runs parallel to the pics on a side, and the other is generated from the set of ten long lines (xl) from the plc array that terminate in the pic. another local pic system clock route comes from the set of ten xl lines in the adjacent plc that is parallel to the side of the array on which the pic resides. the fourth local pic system clock route comes from the set of ten long lines (xl) from the plc array that terminate in the adja- cent pic that is not part of the same pic pair. much like the e1 signals in the plcs that are used to distribute a local clock to the pfu source, the ?th local clock line in each pic comes from local psw signals. this clock signal for each pic is shown in figure 33. one of these ?e local pic system clocks is selected for the system clock signal in the pio. it is used as the pio system clock for both input and output clocking as selected within the pio. all pios in a pic share the same sys- tem clock. pic expressclk the expressclk signal used at the pic latches/ffs comes from the clkcntrl function block that resides in the middle of the side on which the pic resides. a single signal comes from the clkcntrl and is driven by separate buffers onto two expressclk long wires. one of these expressclk signals goes to the pics on the right of (above) the clkcntrl block, and the other expressclk signal goes to the pics on the left of (below) the clkcntrl block on that side. pad a pad b pad c pad d psw[4] psw[5] psw[6] psw[7] pad a pad b pad c pad d psw[4] psw[5] psw[6] psw[7] spine to local clocks to local clocks tpicl tpicr select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 51 data sheet november 2006 orca series 3c and 3t fpgas clock distribution network (continued) expressclk inputs there are four dedicated expressclk pads on each series 3 device: one in the middle of each side. two other user i/o pads can also be used as corner expressclk inputs, one on the lower-left corner, and one on the upper-right corner. the corner expressclk pads feed the expressclk to the two sides of the array that are adjacent to that corner, always driving the same signal in both directions. the expressclk route from the middle pad and from the corner pad associ- ated with that side are multiplexed and can be glitch- lessly stopped/started under user control using the stopclk feature of the clkcntrl function block (described under special function blocks) on that side. the expressclk output of the programmable clock manager ( pcm ) is programmably connected to the cor- ner expressclk routes. pcm blocks are found in the same corners as the corner expressclk signals and are described in the special function blocks section. the expressclk structure is shown in figure 34 ( pcm blocks are not shown). 5-5802(f) note: all multiplexers are set during con?uration. figure 34. expressclk and fast clock distribution selecting clock input pins any user i/o pin on an orca fpga can be used as a fast, low-skew system clock input. since the four dedi- cated expressclk inputs can only be used to distribute global signals into the fpga, these pins should be selected ?st as clock pins. within the interquad region of the device, these clocks sourced by the expressclk inputs are called fast clocks. choosing the next clock pin is completely arbitrary, but using a pin that is near the center of an edge of the device will provide the low- est skew system clock network. the pin-to-pin timing numbers in the timing characteristics section assume that the clock pin is in one of the pics at the center of any side of the device next to an expressclk pad. for actual timing characteristics for a given clock pin, use the timing analyzer results from isplever. to select subsequent clock pins, certain rules should be followed. as discussed in the programmable input/ output cells section, pics are grouped into adjacent pairs. each of these pairs contains eight i/os, but only one of the eight i/os in a pic pair can be routed directly onto a system clock spine. therefore, to achieve top performance, the next clock input chosen should not be one of the pins from a pic pair previously used for a clock input. if it is necessary to have a second input in the same pic pair route onto global system clock rout- ing, the input can be routed to a free clock spine using the pic switching segment (psw) connections to the clock spine network at some small sacri?e in speed. alternatively, if global distribution of the secondary clock is not required, the signal can be routed on long lines (xl) and input to the pfu clock input without using a clock spine. another rule for choosing clock pins has to do with the alternating nature of clock spine connections to the xl and pxl routing segments. starting at the left side of the device, the ?st vertical clock spine from the top connects to hxl[0] (horizontal xl[0]), and the ?st verti- cal clock spine from the bottom connects to hxl[5] in all plc rows. the next vertical clock spine from the top connects to hxl[1], and the next one from the bottom connects to hxl[6]. this progression continues across the device, and after a spine connects to hxl[9], the next spine connects to hxl[0] again. similar connec- tions are made from horizontal clock spines to vxl (ver- tical xl) lines from the top to the bottom of the device. because the orca series 3 clock routing only requires the use of an xl line in every other row or col- umn, even two inputs chosen 20 plcs apart on the same xl line will not con?ct, but it is always better to avoid these choices, if possible. the fast clock spines in the interquad routing region also connect to xl[8] and xl[9] for each set of xl lines, so it is better to avoid user i/os that connect to xl[8] or xl[9] when a fast clock is used that might share one of these connections. another reason to use the fast clock spines is that since they use only the xl[9:8] lines, they will not con- ?ct with internal data buses which typically use xl[7:0]. for more details on clock selection, refer to application notes on clock distribution in orca series 3 devices. expressclks to pios fast clocks expressclk pads clkcntrl block select devices have been discontinued. see ordering information section for product status.
52 52 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas special function blocks special function blocks in the series 3 provide extra capabilities beyond general fpga operation. these blocks reside in the corners and mids (middle inter- quad areas) of the fpga array. single function blocks most of the special function blocks perform a speci? dedicated function. these functions are data/con?ura- tion readback control, global 3-state control (ts_all), internal oscillator generation, global set/reset (gsrn), and start-up logic. readback logic the readback logic is located in the upper right corner of the fpga and can be enabled via a bit stream option or by instantiation of a library readback component. readback is used to read back the con?uration data and, optionally, the state of the pfu outputs. a read- back operation can be done while the fpga is in nor- mal system operation. the readback operation cannot be daisy-chained. to use readback, the user selects options in the bit stream generator in the isplever development system. table 12 provides readback options selected in the bit stream generator tool. the table provides the number of times that the con?uration data can be read back. this is intended primarily to give the user control over the security of the fpgas con?uration program. the user can prohibit readback (0), allow a single readback (1), or allow unrestricted readback (u). readback can be performed via the series 3 micropro- cessor interface ( mpi ) or by using dedicated fpga readback controls. if the mpi is enabled, readback via the dedicated fpga readback logic is disabled. read- back using the mpi is discussed in the microprocessor interface ( mpi ) section. the pins used for dedicated readback are readback data (rd_data), read con?uration ( rd_cfg ), and con?uration clock (cclk). a readback operation is initiated by a high-to-low transition on rd_cfg . the rd_cfg input must remain low during the readback operation. the readback operation can be restarted at frame 0 by driving the rd_cfg pin high, applying at least two rising edges of cclk, and then driving rd_cfg low again. one bit of data is shifted out on rd_data at the rising edge of cclk. the ?st start bit of the readback frame is transmitted out several cycles after the ?st rising edge of cclk after rd_cfg is input low (see the readback timing characteristics table in the timing characteristics section). to be certain of the start of the readback frame, the data can be monitored for the 01 frame start bit pair. readback can be initiated at an address other than frame 0 via the new microprocessor interface ( mpi ) control registers (see the microprocessor interface ( mpi ) section for more information). in all cases, read- back is performed at sequential addresses from the start address. it should be noted that the rd_data output pin is also used as the dedicated boundary-scan output pin, tdo. if this pin is being used as tdo, the rd_data output from readback can be routed internally to any other pin desired. the rd_cfg input pin is also used to control the global 3-state (ts_all) function. before and during con?uration, the ts_all signal is always driven by the rd_cfg input and readback is disabled. after con- ?uration, the selection as to whether this input drives the readback or global 3-state function is determined by a set of bit stream options. if used as the rd_cfg input for readback, the internal ts_all input can be routed internally to be driven by any input pin. table 12. readback options option function 0 prohibit readback 1 allow one readback only u allow unrestricted number of readbacks select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 53 data sheet november 2006 orca series 3c and 3t fpgas special function blocks (continued) the readback frame contains the con?uration data and the state of the internal logic. during readback, the value of all registered pfu and pic outputs can be captured. the following options are allowed when doing a capture of the pfu outputs. 1. do not capture data (the data written to the rams, usually 0, will be read back). 2. capture data upon entering readback. 3. capture data based upon a con?urable signal internal to the fpga. if this signal is tied to logic 0, capture rams are written continuously. 4. capture data on either options 2 or 3 above. the readback frame has an identical format to that of the con?uration data frame, which is discussed later in the con?uration data format section. if lut mem- ory is not used as ram and there is no data capture, the readback data (not just the format) will be identical to the con?uration data for the same frame. this eases a bitwise comparison between the con?uration and readback data. the con?uration header, including the length count ?ld, is not part of the readback frame. the readback frame contains bits in locations not used in the con?uration. these locations need to be masked out when comparing the con?uration and readback frames. the development system optionally provides a readback bit stream to compare to readback data from the fpga. also note that if any of the luts are used as ram and new data is written to them, these bits will not have the same values as the original con?uration data frame either. global 3-state control (ts_all) to increase the testability of the orca series fpgas, the global 3-state function (ts_all) disables the device. the ts_all signal is driven from either an external pin or an internal signal. before and during con?uration, the ts_all signal is driven by the input pad rd_cfg . after con?uration, the ts_all signal can be disabled, driven from the rd_cfg input pad, or driven by a general routing signal in the upper right cor- ner. before con?uration, ts_all is active-low; after con?uration, the sense of ts_all can be inverted. the following occur when ts_all is activated: 1. all of the user i/o output buffers are 3-stated, the user i/o input buffers are pulled up (with the pull- down disabled), and the input buffers are con?ured with ttl input thresholds (or3cxx only). 2. the tdo/rd_data output buffer is 3-stated. 3. the rd_cfg , reset , and prgm input buffers remain active with a pull-up. 4. the done output buffer is 3-stated, and the input buffer is pulled up. internal oscillator the internal oscillator resides in the lower left corner of the fpga array. it has output clock frequencies of 1.25 mhz and 10 mhz. the internal oscillator is the source of the internal cclk used for con?uration. it may also be used after con?uration as a general- purpose clock signal. global set/reset (gsrn) the gsrn logic resides in the lower right corner of the fpga. gsrn is an invertible, default, active-low signal that is used to reset all of the user-accessible latches/ ffs on the device. gsrn is automatically asserted at powerup and during con?uration of the device. the timing of the release of gsrn at the end of con?- uration can be programmed in the start-up logic described below. following con?uration, gsrn may be connected to the reset pin via dedicated routing, or it may be connected to any signal via normal routing. within each pfu and pio, individual ffs and latches can be programmed to either be set or reset when gsrn is asserted. a new option in series 3 allows individual pfus and pios to turn off the gsrn signal to its latches/ffs after con?uration. the reset input pad has a special relationship to gsrn. during con?uration, the reset input pad always initiates a con?uration abort, as described in the fpga states of operation section. after con?ura- tion, the global set/reset signal (gsrn) can either be disabled (the default), directly connected to the reset input pad, or sourced by a lower-right corner signal. if the reset input pad is not used as a global reset after con?uration, this pad can be used as a normal input pad. select devices have been discontinued. see ordering information section for product status.
54 54 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas special function blocks (continued) start-up logic the start-up logic block is located in the lower right cor- ner of the fpga. this block can be con?ured to coor- dinate the relative timing of the release of gsrn, the activation of all user i/os, and the assertion of the done signal at the end of con?uration. if a start-up clock is used to time these events, the start-up clock can come from cclk, or it can be routed into the start- up block using lower right corner routing resources. these signals are described in the start-up subsection of the fpga states of operation section. clock control (clkcntrl) and stopclk there is one clkcntrl block in the mid section of the interquad routing on each side of the fpga. this block is used to selectively distribute the fast clock to the plc array and the left (top) and right (bottom) expressclks (eckl and eckr) to the side of the array on which the clkcntrl block resides. the source clock for the clkcntrl block comes either from the expressclk pad at the middle of the side of the fpga or from the corner expressclk route that comes from the corner expressclk pad (at the lower left or upper right of the device, whichever is closer). the programmable clock manager expressclk output can also be sourced to this corner routing for distribution at the two closest clkcntrl blocks. each clkcntrl block also features an invertible stopclk shutoff input that is available from local rout- ing. this feature may be used to glitchlessly stop and start the clock at the three outputs of each clkcntrl block and has the option of doing so on either the rising or falling edge of the clock. when the clock is halted based on its rising edge, it stops and stays at v dd . when it is stopped based on its falling edge, it stops and stays at gnd. if the stopclk shutoff signal meets the clkcntrl setup and hold times, the clock is stopped on the second clock cycle after the shutoff sig- nal. a diagram of the bottom clkcntrl block and stopclk timing is shown in figure 35. 5-5981(f) notes: clkcntrl output clocks are expressclk left and right and fast clock. clock shutoff shown active-high acting on clock falling edge. figure 35. top clkcntrl function block corner expressclk clock shutoff expressclk right expressclk left fast clock clock shutoff off_set off_hld off_set off_hld clkcntrl output clocks select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 55 data sheet november 2006 orca series 3c and 3t fpgas special function blocks (continued) boundary scan the increasing complexity of integrated circuits (ics) and ic packages has increased the dif?ulty of testing printed-circuit boards (pcbs). to address this testing problem, the ieee standard 1149.1/d1 ( ieee standard test access port and boundary-scan architecture) is implemented in the orca series of fpgas. it allows users to ef?iently test the interconnection between integrated circuits on a pcb as well as test the inte- grated circuit itself. the ieee 1149.1/d1 standard is a well-de?ed protocol that ensures interoperability among boundary-scan (bscan) equipped devices from different vendors. the ieee 1149.1/d1 standard de?es a test access port (tap) that consists of a four-pin interface with an optional reset pin for boundary-scan testing of inte- grated circuits in a system. the orca series fpga provides four interface pins: test data in (tdi), test mode select (tms), test clock (tck), and test data out (tdo). the prgm pin used to recon?ure the device also resets the boundary-scan logic. the user test host serially loads test commands and test data into the fpga through these pins to drive out- puts and examine inputs. in the con?uration shown in figure 36, where boundary scan is used to test ics, test data is transmitted serially into tdi of the ?st bscan device (u1), through tdo/tdi connections between bscan devices (u2 and u3), and out tdo of the last bscan device (u4). in this con?uration, the tms and tck signals are routed to all boundary-scan ics in parallel so that all boundary-scan components operate in the same state. in other con?urations, mul- tiple scan paths are used instead of a single ring. when multiple scan paths are used, each ring is indepen- dently controlled by its own tms and tck signals. figure 37 provides a system interface for components used in the boundary-scan testing of pcbs. the three major components shown are the test host, boundary- scan support circuit, and the devices under test (duts). the duts shown here are orca series fpgas with dedicated boundary-scan circuitry. the test host is normally one of the following: automatic test equipment (ate), a workstation, a pc, or a micropro- cessor. 5-5972(f) key: bsc = boundary-scan cell, bdc = bidirectional data cell, and dcc = data control cell. figure 36. printed-circuit board with boundary- scan circuitry tdi tms tck tdo tdi tdo tms tck u2 net a net b net c plc array bdc bsc p_in p_ts scan out scan in pr[ij] dcc p_out bdc bsc p_in p_out p_ts pl[ij] dcc scan in scan out bdc dcc bsc p_in p_out p_ts scan out pb[ij] scan in tdo tck tms tdi tapc bypass register instruction register bdc dcc bsc p_in p_out p_ts scan out scan in pt[ij] see enlarged view below s tdi tdo tms tck u3 tdi tdo tms tck u4 tdi tdo tms tck u2 select devices have been discontinued. see ordering information section for product status.
56 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas special function blocks (continued) 5-6765(f) figure 37. boundary-scan interface d[7:0] intr micro- processor d[7:0] ce ra r/w dav int sp tms0 tck tdi tdo tdi tms tck tdo orca series fpga tdi orca series fpga tms tck tdo tdi tms tck tdo orca series fpga boundary- scan master (bsm) (dut) (dut) (dut) the boundary-scan support circuit shown in figure 37 is the 497aa boundary-scan master (bsm). the bsm off-loads tasks from the test host to increase test throughput. to interface between the test host and the duts, the bsm has a general microprocessor interface and provides parallel-to-serial/serial-to-parallel conver- sion, as well as three 8k data buffers. the bsm also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis register. the pc- based boundary-scan test card/software allows a user to quickly prototype a boundary-scan test setup. boundary-scan instructions the orca series boundary-scan circuitry is used for three mandatory ieee 1149.1/d1 tests (extest, sample/preload, bypass), the optional ieee 1149.1/d1 idcode instruction, and ?e orca -de?ed instructions. the 3-bit wide instruction register supports the nine instructions listed in table 13, where the use of psr1 or usercode is selectable by a bit stream option. table 13. boundary-scan instructions code instruction 000 extest 001 plc scan ring 1 (psr1)/usercode 010 ram write (ram_w) 011 idcode 100 sample/preload 101 plc scan ring 2 (psr2) 110 ram read (ram_r) 111 bypass select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 57 data sheet november 2006 orca series 3c and 3t fpgas special function blocks (continued) the external test (extest) instruction allows the inter- connections between ics in a system to be tested for opens and stuck-at faults. if an extest instruction is performed for the system shown in figure 36, the con- nections between u1 and u2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether the same value is seen at the other device. this is deter- mined by shifting 2 bits of data for each pin (one for the output value and one for the 3-state value) through the bsr until each one aligns to the appropriate pin. then, based upon the value of the 3-state signal, either the i/o pad is driven to the value given in the bsr, or the bsr is updated with the input value from the i/o pad, which allows it to be shifted out tdo. the sample/preload instruction is useful for sys- tem debugging and fault diagnosis by allowing the data at the fpgas i/os to be observed during normal operation or written during test operation. the data for all of the i/os is captured simultaneously into the bsr, allowing them to be shifted-out tdo to the test host. since each i/o buffer in the pics is bidirectional, two pieces of data are captured for each i/o pad: the value at the i/o pad and the value of the 3-state control sig- nal. for preload operation, data is written from the bsr to all of the i/os simultaneously. there are ?e orca -de?ed instructions. the plc scan rings 1 and 2 (psr1, psr2) allow user-de?ed internal scan paths using the plc latches/ffs. the ram_write enable (ram_w) instruction allows the user to serially con?ure the fpga through tdi. the ram_read enable (ram_r) allows the user to read back ram contents on tdo after con?uration. the idcode instruction allows the user to capture a 32-bit identi?ation code that is unique to each device and serially output it at tdo. the idcode format is shown in table 14. table 14. boundary-scan id code * plc array size of fpga, reverse bit order. note: table assumes version 0. device version (4 bits) part* (10 bits) family (6 bits) manufacturer (11 bits) lsb (1 bit) or3t20 0000 0011000000 110000 00000011101 1 or3t30 0000 0111000000 110000 00000011101 1 or3t55 0000 0100100000 110000 00000011101 1 or3c/t80 0000 0110100000 110000 00000011101 1 or3t125 0000 0011100000 110000 00000011101 1 select devices have been discontinued. see ordering information section for product status.
58 58 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas special function blocks (continued) orca boundary-scan circuitry the orca series boundary-scan circuitry includes a test access port controller (tapc), instruction register (ir), boundary-scan register (bsr), and bypass regis- ter. it also includes circuitry to support the four pre- de?ed instructions. figure 38 shows a functional diagram of the boundary- scan circuitry that is implemented in the orca series. the input pins (tms, tck, and tdi) locations vary depending on the part, and the output pin is the dedi- cated tdo/rd_data output pad. test data in (tdi) is the serial input data. test mode select (tms) controls the boundary-scan test access port controller (tapc). test clock (tck) is the test clock on the board. the bsr is a series connection of boundary-scan cells (bscs) around the periphery of the ic. each i/o pad on the fpga, except for cclk, done, and the boundary- scan pins (tck, tdi, tms, and tdo), is included in the bsr. the ?st bsc in the bsr (connected to tdi) is located in the ?st pic i/o pad on the left of the top side of the fpga (pta pic). the bsr proceeds clockwise around the top, right, bottom, and left sides of the array. the last bsc in the bsr (connected to tdo) is located on the top of the left side of the array (pl1d). the bypass instruction uses a single ff, which resyn- chronizes test data that is not part of the current scan operation. in a bypass instruction, test data received on tdi is shifted out of the bypass register to tdo. since the bsr (which requires a two ff delay for each pad) is bypassed, test throughput is increased when devices that are not part of a test operation are bypassed. the boundary-scan logic is enabled before and during con?uration. after con?uration, a con?uration option determines whether or not boundary-scan logic is used. the 32-bit boundary-scan identi?ation register con- tains the manufacturers id number, unique part num- ber, and version (as described earlier). the identi?ation register is the default source for data on tdo after reset if the tap controller selects the shift- data-register (shift-dr) instruction. if boundary scan is not used, tms, tdi, and tck become user i/os, and tdo is 3-stated or used in the readback operation. an optional usercode is available if the boundary- scan psr1 instruction is not used. the selection between psr1 and usercode is a con?uration option and can be performed in isplever. the user- code is an 11-bit value that the user can set during device con?uration and can be written to and read from the fpga via the boundary-scan logic. the usercode value replaces the manufacturer ?ld of the boundary-scan id code when the usercode instruction is issued, allowing users to have con?ured devices identi?d in a user-de?ed manner. the manu- facturer id ?ld remains available when the idcode instruction is issued. 5-5768(f) figure 38. orca series boundary-scan circuitry functional diagram tap controller tms tck boundary-scan register psr2 register (plcs) bypass register data mux instruction decoder instruction register m u x reset clock ir shift-ir update-ir pur tdo select enable reset clock dr shift-dr update-dr tdi data registers psr1 register (plcs) configuration register (ram_r, ram_w) prgm i/o buffers v dd v dd v dd v dd idcode register select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 59 data sheet november 2006 orca series 3c and 3t fpgas special function blocks (continued) orca series tap controller (tapc) the orca series tap controller (tapc) is a 1149.1/ d1 compatible test access port controller. the 16 jtag state assignments from the ieee 1149.1/d1 speci?a- tion are used. the tapc is controlled by tck and tms. the tapc states are used for loading the ir to allow three basic functions in testing: providing test stimuli (update-dr), test execution (run-test/idle), and obtaining test responses (capture-dr). the tapc allows the test host to shift in and out both instructions and test data/results. the inputs and outputs of the tapc are provided in the table below. the outputs are primarily the control signals to the instruction register and the data register. table 15. tap controller input/outputs the tapc generates control signals that allow capture, shift, and update operations on the instruction and data registers. in the capture operation, data is loaded into the register. in the shift operation, the captured data is shifted out while new data is shifted in. in the update operation, either the instruction register is loaded for instruction decode, or the boundary-scan register is updated for control of outputs. the test host generates a test by providing input into the orca series tms input synchronous with tck. this sequences the tapc through states in order to perform the desired function on the instruction register or a data register. figure 39 provides a diagram of the state transitions for the tapc. the next state is deter- mined by the tms input value. 5-5370(f) figure 39. tap controller state transition diagram symbol i/o function tms i test mode select tck i test clock pur i powerup reset prgm i bscan reset treset o test logic reset select o select ir (high); select-dr (low) enable o test data out enable capture-dr o capture/parallel load-dr capture-ir o capture/parallel load-ir shift-dr o shift data register shift-ir o shift instruction register update-dr o update/parallel load-dr update-ir o update/parallel load-ir select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 1 0 0 10 run-test/ idle 1 test-logic- reset select- ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 1 0 10 00 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 11 0 select devices have been discontinued. see ordering information section for product status.
60 60 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas special function blocks (continued) boundary-scan cells figure 40 is a diagram of the boundary-scan cell (bsc) in the orca series pics. there are four bscs in each pic: one for each pad, except as noted above. the bscs are connected serially to form the bsr. the bsc controls the functionality of the in, out, and 3-state sig- nals for each pad. the bsc allows the i/o to function in either the normal or test mode. normal mode is de?ed as when an out- put buffer receives input from the plc array and pro- vides output at the pad or when an input buffer provides input from the pad to the plc array. in the test mode, the bsc executes a boundary-scan operation, such as shifting in scan data from an upstream bsc in the bsr, providing test stimuli to the pad, capturing test data at the pad, etc. the primary functions of the bsc are shifting scan data serially in the bsr and observing input (p_in), output (p_out), and 3-state (p_ts) signals at the pads. the bsc consists of two circuits: the bidirectional data cell is used to access the input and output data, and the direction control cell is used to access the 3-state value. both cells consist of a ?p-?p used to shift scan data which feeds a ?p-?p to control the i/o buffer. the bidirectional data cell is connected serially to the direc- tion control cell to form a boundary-scan shift register. the tapc signals (capture, update, shiftn, treset, and tck) and the mode signal control the operation of the bsc. the bidirectional data cell is also controlled by the high out/low in (holi) signal generated by the direction control cell. when holi is low, the bidirec- tional data cell receives input buffer data into the bsc. when holi is high, the bsc is loaded with functional data from the plc. the mode signal is generated from the decode of the instruction register. when the mode signal is high (extest), the scan data is propagated to the output buffer. when the mode signal is low (bypass or sample), functional data from the fpgas internal logic is propagated to the output buffer. the boundary-scan description language (bsdl) is provided for each device in the orca series of fpgas on the isplever cd. the bsdl is generated from a device pro?e, pinout, and other boundary-scan infor- mation. 5-2844(f figure 40. boundary-scan cell d q d q d q d q scan in p_out holi bidirectional data cell i/o buffer direction control cell mode update/tck scan out tck shiftn/capture p_ts p_in pad_in pad_ts pad_out 0 1 0 1 0 1 0 1 0 1 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 61 data sheet november 2006 orca series 3c and 3t fpgas special function blocks (continued) boundary-scan timing to ensure race-free operation, data changes on speci? clock edges. the tms and tdi inputs are clocked in on the rising edge of tck, while changes on tdo occur on the falling edge of tck. in the execution of an extest instruction, parallel data is output from the bsr to the fpga pads on the falling edge of tck. the maximum fre- quency allowed for tck is 10 mhz. figure 41 shows timing waveforms for an instruction scan operation. the diagram shows the use of tms to sequence the tapc through states. the test host (or bsm) changes data on the falling edge of tck, and it is clocked into the dut on the rising edge. 5-5971(f) figure 41. instruction register scan timing diagram tck tms tdi run-test/idle run-test/idle exit1-ir exit2-ir update-ir select-dr-scan capture-ir select-ir-scan test-logic-reset shift-ir pause-ir shift-ir exit1-ir select devices have been discontinued. see ordering information section for product status.
62 62 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas microprocessor interface (mpi) the series 3 fpgas have a dedicated synchronous microprocessor interface function block (see figure 42). the mpi is programmable to operate with powerpc mpc800 series microprocessors and intel * i960 * j core processors; see table 16 and table 17, respectively, for compatible processors. the mpi imple- ments an 8-bit interface to the host processor ( pow- erpc or i960 ) that can be used for con?uration and readback of the fpga as well as for user-de?ed data processing and general monitoring of fpga function. in addition to dedicated-function registers, the micro- processor interface allows for the control of up to 16 user registers (ram or ?p-?ps) in the fpga logic. a synchronous/asynchronous handshake procedure is used to control transactions with user logic in the fpga array. there is also capability for the fpga logic to interrupt the host processor either by a hard interrupt or by having the host processor poll the microprocessor interface. the control portion of the microprocessor interface is available following powerup of the fpga if the mode pins specify mpi mode, even if the fpga is not yet con- ?ured. the mode pin (m[2:0]) settings can be found in the fpga con?uration modes section of this data sheet, and the setup and use of the mpi for con?ura- tion is discussed in the mpi setup and control subsec- tion. for postcon?uration use, the mpi must be included in the con?uration bit stream by using an mpi library element in your design from the orca macro library, or by setting the mp_user bit of the mpi con- ?uration control register prior to the start of con?ura- tion ( mpi registers are discussed later). * intel and i960 are registered trademarks of intel corporation. 5-5806(f) figure 42. mpi block diagram done rd_data init d7 d7in d7out d6 d6in d6out d5 d5in d5out d4 d4in d4out d3 d3in d3out d2 d2in d2out d1 d1in d1out d0 d0in d0out orcaorca 3c/txxx mpi status register scratchpad register readback data register readback addr register control registers part id registers reset rd_cfg prgm gsr irq to gsr block to fpga routing user_start user_end wr_ctrl a[3:0] rdyrcv clk ads ale w/r i960 logic rd/wr bt ts clkout ta powerpc logic decode/control powerpc only a4 a3 a2 a1 a0 rd cs0 cs1 cclk m3 m2 m1 m0 mpi_irq mpi_ack mpi_clk mpi_strb mpi_ale mpi_rw mpi_b1 to fpga routing d[7:0]in d[7:0]out device pad i/o buffer select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 63 data sheet november 2006 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) powerpc system in figure 43, the orca fpga is a memory-mapped peripheral to the powerpc processor. the powerpc interface uses separate address and data buses and has several control lines. the orca chip select lines, cs0 and cs1, are each connected to an address line coming from the powerpc . in this manner, the fpga is capable of a transaction with the powerpc whenever the address line connected to cs0 is low, the address line for cs1 is high, and there is a valid address on powerpc address lines a[27:31]. other forms of selec- tion are possible by using the fpga chip selects in a different way. for example, powerpc address bits a[0:26] could be decoded to select cs0 and cs1, or if the fpga is the only peripheral to the powerpc , cs0 and cs1 could be tied low and high, respectively, to cause them to always be selected. if the mpi is not used for fpga con?uration, decoding logic can be implemented internal or external to the fpga. if logic internal to the fpga is used, the chip selects must be routed out on an output pin and then connected exter- nally to cs0 and/or cs1. if the mpi is to be used for con?uration, any decode logic used must be imple- mented external to the fpga since the fpga logic has not been con?ured yet. 5-5761(f) note: fpga shown as a memory-mapped peripheral using cs0 and cs1. other decoding schemes are possible using cs0 and/or cs1. figure 43. powerpc /mpi the basic ?w of a transaction on the powerpc / mpi interface is given below. pin descriptions are shown in table 16 and timing is shown in the timing characteris- tics section of this data sheet. for both read and write transactions, the address, chip select, and read/write (read high, write low) signals are set up at the fpga pins by the powerpc . the powerpc then asserts its transfer start signal ( ts ) low. data is available to the mpi during a write at the rising clock edge after the clock cycle during which ts is low. the transfer is acknowledged to the powerpc by the low asser tion of the t a signal. the mpi powerpc interface does not support burst transfers, so the burst inhibit signal, bi , is also asserted low during the transfer acknowledge . the same process applies to a read from the mpi except that the read data is expected at the fpga data pins by the powerpc at the rising edge of the clock when t a is low. the mpi only drives t a low for one clock cycle. interrupt requests can be sent to the powerpc asyn- chronously to the read/write process. interrupt requests are sourced by the user-logic in the fpga. the mpi will assert the request to the powerpc as a direct interrupt signal and/or a pollable bit in the mpi status register (discussed in the mpi setup and control section). the mpi will continue to assert the interrupt request until the user-logic deasserts its interrupt request signal. table 16 . powerpc /mpi con?uration dout cclk d[7:0] a[4:0] mpi_clk mpi_rw mpi_ack mpi_bi mpi_irq mpi_strb cs0 cs1 hdc ldc d[7:0] a[27:31] clkout rd/wr ta bi irq x ts a26 a25 to daisy- chained devices powerpc orca 8 fpga series 3 done init powerpc signal orca pin name mpi i/o function d[0:7] d[7:0] i/o 8-bit data bus a[27:31] a[4:0] i 5-bit mpi address bus ts rd/mpi_strb i transfer start signal cs0 i active-low mpi select cs1 i active-high mpi select clkout a7/mpi_clk i powerpc interface clock rd/ wr a8/mpi_rw i read (high)/write (low) signal t a a9/ mpi_a ck o active-low transfer acknowledge signal bi a10/ mpi_bi o active-low burst transfer inhibit signal any of irq [7:0] a11/ mpi_irq o active-low interrupt request signal select devices have been discontinued. see ordering information section for product status.
64 64 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) i960 system figure 44 shows a schematic for connecting the orca mpi to supported i960 processors. in the ?ure, the fpga is shown as the only peripheral, with the fpga chip select lines, cs0 and cs1, tied low and high, respectively. the i960 address and data are multi- plexed onto the same bus. this precludes memory mapping of the fpga in the i960 memory space of a multiperipheral system without some form of address latching to capture and hold the address signals to drive the cs0 and/or cs1 signals. multiple address sig- nals could also be decoded and latched to drive the cs0 and/or cs1 signals. if the mpi is not used for fpga con?uration, decoding/latching logic can be implemented internal or external to the fpga. if logic internal to the fpga is used, the chip selects must be routed out an output pin and then connected externally to cs0 and/or cs1. if the mpi is to be used for con?u- ration, any decode/latch logic used must be imple- mented external to the fpga since the fpga logic has not been con?ured yet. 5-5762(f) note: fpga shown as only system peripheral with ?ed-chip select signals. for multiperipheral systems, address decoding and/or latching can be used to implement chip selects. figure 44. i960 /mpi the basic ?w of a transaction on the i960 / mpi inter- face is given below. pin descriptions are shown in table 17, and timing is shown in the orca timing characteristics section of this data sheet. for both read and write transactions, the address latch enable (ale) is set up by the i960 at the fpga to the falling edge of the clock. the address, byte enables, chip selects, and read/write (read low, write high) signals are normally set up at the fpga pins by the i960 at the next rising edge of the clock. at this same rising clock edge, the i960 asserts its address/data strobe ( ads ) low. data is available to the mpi during a write at the rising clock edge of the following clock cycle. the transfer is acknowledged to the i960 by the low assertion of the ready/recover ( rd yrcv ) signal. the same process applies to a read from the mpi except that the read data is expected at the fpga data pins by the i960 at the rising edge of the clock when rd yrcv is low. the mpi only drives rd yrcv low for one clock cycle. interrupts can be sent to the i960 asynchronously to the read/write process. interrupt requests are sourced by the user-logic in the fpga. the mpi will assert the request to the i960 as a direct interrupt signal and/or a pollable bit in the mpi status register (discussed in the mpi setup and control section). the mpi will continue to assert the interrupt request until the user-logic deas- serts its interrupt request signal. table 17. i960/mpi configuration dout cclk d[7:0] mpi_clk mpi_rw mpi_ack mpi_irq mpi_ale mpi_be1 hdc ldc to daisy- chained devices orca 8 fpga series 3 done init ad[7:0] clkin w/r rdyrcv xint x ale be1 i960 cs1 cs0 i960 system clock v dd mpi_be0 be0 mpi_strb ads i960 signal orca pin name mpi i/o function ad[7:0] d[7:0] i/o multiplexed 5-bit address/ 8-bit data bus. the address appears on d[4:0]. ale rdy/rclk/ mpi_ale i address latch enable used to capture address from ad[4:0] on falling edge of clock. ads rd / mpi_strb i address/data strobe to indicate start of transac- tion. cs0 i active-low mpi select. cs1 i active-high mpi select. system clock a7/ mpi_clk i i960 system clock. this clock is sourced by the system and not the i960 . w/ r a8/mpi_rw i write (high)/read (low) signal. rd yrcv a9/ mpi_a ck o active-low ready/recover signal indicating acknowl- edgment of the transac- tion. any of xint [7:0] a11/ mpi_irq o active-low interrupt request signal. be0 a0/ mpi_be0 i byte-enable 0 used as address bit 0 in i960 8-bit mode. be1 a1/ mpi_be1 i byte-enable 1 used as address bit 1 in i960 8-bit mode. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 65 data sheet november 2006 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) mpi interface to fpga the mpi interfaces to the user-programmable fpga logic using a 4-bit address, read/write control signal, interrupt request signal, and user start and user end handshake signals. timing numbers are provided so that the user-logic data transfers can be performed syn- chronously with the host processor ( powerpc or i960 ) interface clock or asynchronously. table 18 shows the internal interface signals between the mpi and the fpga user-programmable logic. all of the signals are connected to the mpi in the upper-left corner of the device except for the d[7:0] and clk signals that come directly from the i/o pin. the 4-bit addressing from the mpi to the plcs allows for up to 16 locations to be addressed by the host pro- cessor. the user address space of the mpi does not address any hard register. rather, the user is free to construct registers from ffs, latches, or ram that can be selected by the addressing. alternately, the decoded address signals may be used as control signals for other functions such as state machines or timers. the transaction sequence between the mpi and the user-logic is as follows. when the host processor ini- tiates a transaction as discussed in the preceding sec- tions, the mpi outputs the 4-bit user address (ua[3:0]) and the read/write control signal ( urd wr , which is read-high, write-low regardless of host processor), and then asserts the user start signal, ustart. during a write from the host processor, the user logic can accept data written by the host processor from the d[7:0] pins once the ustart signal is asserted. the user logic ends a transaction by asserting an active-high user end (uend) signal to the mpi . the mpi will insert wait-states in the host processor bus cycles, holding the host processor until the user- logic completes its task and returns a uend signal, upon which the mpi generates an acknowledge signal. if the host processor is reading from the fpga, the user logic must have the read data available on the d[7:0] pins of the fpga when the uend signal is asserted. if the user logic is fast or if the mpi user address is being decoded for use as a control signal, the mpi transaction time can be minimized by routing the ustart signal directly to the uend input of the mpi . the timing section of this data sheet contains a parameter table with delay, setup, and hold timing requirements to operate the user-logic either synchro- nously or asynchronously with the mpi host interface clock. the user-logic may also assert an active-low interrupt request ( uirq ) to the mpi , which, in turn, asserts an interrupt to the host processor. assertion of an inter- rupt request is asynchronous to the host processor clock and any read or write transaction occurring in the mpi . the user-logic is responsible for providing any required interrupt vectors for the host processor, and the user-logic must deassert the interrupt request once serviced. if the interrupt request is not deasserted in the user logic, it will continue to be asserted to the host processor via the mpi_irq pin. table 18. mpi internal interface signals signal mpi i/o function ua[3:0] o user logic address . addresses up to 16 unique user registers or use as control signals. urdwrn o user logic read/write control signal . high indicates a read from user logic by the host processor, low indicates a write to user-logic by the host processor. ustart o active-high user start signal . indicates the start of an mpi transaction between the host processor and the user logic. uend i active-high user end signal . indicates that the user-logic is ?ished with the current mpi transaction. uirq i active-low interrupt. sends request from the user-logic to the host processor. d[7:0] fpga i/o user data. eight data bits come directly from the fpga pins?ot through the mpi . mpi_clk fpga i mpi clock. the mpi clock is sourced by the host processor and comes directly from the fpga pin?ot through the mpi . select devices have been discontinued. see ordering information section for product status.
66 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) mpi setup and control the mpi has a series of addressable registers that provide mpi control and status, con?uration and readback data transfer, fpga device identi?ation, and a dedicated user scratchpad register. all registers are 8 bits wide. the address map for these registers and the user-logic address space are shown in table 19, followed by descriptions of the register and bit functions. note that for all registers, the most signi?ant bit is bit 7, and the least signi?ant bit is bit 0. table 19. mpi setup and control registers control register 1 the mpi control register 1 is a read/write register. the host processor writes a control byte to con?ure the mpi . it is readable by the host processor to verify the status of control bits previously written. table 20. mpi setup and control registers descriptions address (hex) register 00 control register 1. 01 control register 2. 02 scratchpad register. 03 status register. 04 con?uration/readback data register. 05 readback address register 1 (bits [7:0]). 06 readback address register 2 (bits [15:8]). 07 device id register 1 (bits [7:0]). 08 device id register 2 (bits [15:8]). 09 device id register 3 (bits [23:16]). 0a device id register 4 (bits [31:24]). 0b?f reserved. 10?f user-de?able address space. bit # description bit 0 gsr input. setting this bit to a 1 invokes a global set/reset on the fpga. the host processor must return this bit to a 0 to remove the gsr signal. gsr does not affect the registers at mpi addresses 0 through f hexadecimal or any con?uration registers. default state = 0. bit 1 reserved. bit 2 reserved. bit 3 reserved. bit 4 reserved. bit 5 rd_cfg input. changing this bit to a 0 after con?uration will initiate readback. the host processor must return this bit to a 1 to remove the rd_cfg signal. since this bit works exactly like the rd_cfg input pin, please see the fpga pin descriptions for more information on this signal. default state = 1. bit 6 reserved. bit 7 prgm input. setting this bit to a 0 causes the fpga to begin con?uration and resets the boundary- scan circuitry. the host processor must return this bit to a 1 to remove the prgm signal. since this bit works exactly like the prgm input pin (except that it does not reset the mpi ), please see the fpga pin descriptions for more information on this signal. default state = 1. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 67 data sheet november 2006 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) scratchpad register the mpi scratchpad register is an 8-bit read/write register with no de?ed operation. it may be used for any user- de?ed function. control register 2 the mpi control register 2 is a read/write register. the host processor writes a control byte to con?ure the mpi . it is readable by the host processor to verify the status of control bits it had previously written. table 21. mpi control register 2 bit # bit name description bit 0 en_irq_cfg enable irq for configuration data request in daisy-chain configuration mode . setting this bit to a 1 prior to con?uration enables the irq signal to go active when new data is requested for con?uration writes or is available for con?uration reads to/from the con?uration data register. a 0 clears the irq enable. this bit is only valid for daisy-chain con?uration. default = 0. bit 1 en_irq_err enable irq for bit stream error . setting this bit to a 1 prior to con?uration enables the irq signal to go active on the occurrence of a bit stream error during con?uration. a 0 clears the irq enable. this bit only has effect while in con?ura- tion mode. default = 0. bit 2 en_irq_usr enable irq from the user fpga space . setting this bit to a 1 allows user-de?ed circuitry in the fpga to generate an interrupt to the host processor by sourcing a logic low on the uirq signal in the user logic. default = 0. bit 3 mp_daisy mpi daisy-chain output enable . setting this bit to a 1 enables daisy-chain output of the con?uration data. see the con?uration section of this data sheet for daisy- chain con?uration details. default = 0. bit 4 mp_hold_bus enable bus holding during daisy-chain configuration mode . setting this bit to a 1 will cause the mpi to wait until the fpga con?uration logic has serialized a byte of con?uration data before acknowledging the transaction. the data is only serialized if the mp_daisy (bit 3 above) control bit is set to 1. if mp_hold_bus is set to 0, the mpi will immediately acknowledge a con?uration data byte transfer. immediate acknowledgment allows the host processor to perform other tasks during fpga con?uration by polling the mpi status register (or by interrupt) and only write con?uration data when the fpga is ready. default = 0. bit 5 mp_user mpi user mode enable . setting this bit to a 1 will enable the mpi for user mode operation. mp_user must be set prior to the fpga done signal going high during con?uration. the mpi may also be enabled for user operation via the con?uration bit stream. default = 0. bit 6 reserved bit 7 reserved select devices have been discontinued. see ordering information section for product status.
68 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) status register the microprocessor interface status register is a read-only register, providing information to the host processor. table 22 . status register con?uration data register the mpi con?uration data register is a writable register in con?uration mode and a readable register in readback mode. for fpga con?uration, this is where the con?uration data bytes are sequentially written by the host pro- cessor. similarly, for readback mode, the mpi provides the readback data bytes in this register for the host proces- sor. readback address register 1 the mpi readback address register 1 is a writable register used to accept the least signi?ant address byte (bits [7:0]) of the con?uration data location to be read back. readback address register 2 the mpi readback address register 2 is a writable register used to accept the most signi?ant address byte (bits [15:8]) of the con?uration data location to be read back. bit # description bit 0 reserved . bit 1 data ready . set by the mpi , a 1 on this bit during con?uration alerts the host processor that the fpga is ready for another byte of con?uration data. during byte-wide readback, the mpi sets this bit to a 1 to tell the host processor that a byte of con?uration data is available for reading. this bit is cleared by a host processor access (read or write) to the con?uration data register. bit 2 irq pending . the mpi sets this bit to 1 to indicate to the host processor that the fpga has a pending interrupt request. this bit may be used for the host processor to poll for interrupts if the mpi_irq pin out- put of the fpga has been masked at the host processor. this bit is set to 0 when the status register is read. interrupt requests from the fpga user space must be cleared in fpga user logic in addition to reading this bit. bits [4:3] bit stream error flags . bits 3 and 4 are set by the mpi to indicate any error during fpga con?ura- tion. see bit 2 of control register 2 for the capability to alert the host processor of an error via the irq signal during con?uration. in the truth table below, bit 3 is the lsb (bit on right). these bits are cleared to 0 when prgm goes active: 00 = no error 01 = id error 10 = checksum error 11 = stop-bit/alignment error bit 5 reserved . bit 6 init . this bit re?cts the binary value of the fpga init pin. bit 7 done . this bit re?cts the binary value of the fpga done pin. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 69 data sheet november 2006 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) device id registers the mpi device id is broken into four registers holding 1 byte each. the device id that is available through the mpi is the same as the boundary-scan id code, except that the device id in the mpi has a reverse bit order. there is no means to overwrite any of the device id as can be done with the boundary-scan id, but the mpi scratchpad register can be used as a personalization register. the format for the entire device id is shown below followed by family and device values and the partitioning of the device id into the four device id registers. table 23. device id code * plc array size of fpga. table 24 shows the family and device values for all parts covered by this data sheet. table 24. series 3 family and device id values table 25 describes the device ids for all parts covered by this data sheet as they are partitioned into the four regis- ters found in the mpi . table 25. orca series 3 device id descriptions version part * family manufacturer msb 4 bits 10 bits 6 bits 11 bits 1 bit example: (first version of or3c80) 0000 0110100000 110000 00000011101 1 part name family id (hex) device id (hex) or3t20 03 0c or3t30 03 0e or3t55 03 12 or3c/t80 03 16 or3t125 03 1c device id register 1 bit 0 logic 1. this bit is always a one. bits [7:1] 0011101, the 7 least signi?ant bits of the manufacturer id. device id register 2 bits [3:0] 0000, the 4 most signi?ant bits of the manufacturer id. bits [7:4] the 4 least signi?ant bits of the 10-bit part number. device id register 3 bits [5:0] the 6 most signi?ant bits of the 10-bit part number. bits [7:6] the 2 least signi?ant bits of the device family code. device id register 4 bits [3:0] the 4 most signi?ant bits of the device family code. bits [7:4] the 4-bit device version code. select devices have been discontinued. see ordering information section for product status.
70 70 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) the orca programmable clock manager ( pcm ) is a special function block that is used to modify or condi- tion clock signals for optimum system performance. some of the functions that can be performed with the pcm are clock skew reduction (both internal and board level), duty-cycle adjustment, clock delay reduction, clock phase adjustment, and clock frequency multipli- cation/division. due to the different capabilities required by customer application, each pcm contains both a pll (phase-locked loop) and a dll (delayed- locked loop) mode. by using plc logic resources in conjunction with the pcm , many other functions, such as frequency synthesis, are possible. there are two pcms on each series 3 device, one in the lower left corner and one in the upper right corner. each can drive two different, but interrelated clock net- works inside the fpga. each pcm can take a clock input from the expressclk pad in its corner or from general routing resources. there are also two input sources that provide feedback to the pcm from the plc array. one of these is a dedicated corner express- clk feedback, and the other is from general routing. each pcm sources two clock outputs, one to the cor- ner expressclk that feeds the clkcntrl blocks on the two sides adjacent to the pcm , and one to the sys- tem clock spine network through general routing. fig- ure 45 shows a high-level block diagram of the pcm . functionality of the pcm is programmed during opera- tion through a read/write interface internal to the fpga array or via the con?uration bit stream. the internal fpga interface comprises write enable and read enable signals, a 3-bit address bus, an 8-bit input (to the pcm ) data bus, and an 8-bit output data bus. there is also a pcm output signal, lock, that indicates a sta- ble output clock state. these signals are used to pro- gram a series of registers to con?ure the pcm functional core for the desired functionality. operation of the pcm is divided into two modes, delay- locked loop (dll) and phase-locked loop (pll). some operations can be performed by either mode and some are speci? to a particular mode. these will be described in each individual mode section. in general, dll mode is preferable to pll mode for the same function because it is less sensitive to input clock noise. in the discussions that follow, the duty cycle is the per- cent of the clock period during which the output clock is high. 5-5828(f) figure 45. pcm block diagram user control signals pcm-fpga interface pcm core functions corner expressclk in general clockin feedback expressclk feedback clock from routing expressclk out system clock out (from general routing) (to general routing) select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 71 data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) pcm registers the pcm contains eight user-programmable registers used for con?uring the pcm s functionality. table 26 shows the mapping of the registers and their functions. see figure 46 for more information on the location of pcm ele- ments that are discussed in the table. the pcm registers are referenced in the discussions that follow. detailed explanations of all register bits are supplied following the functional description of the pcm . table 26. pcm registers address function 0 divider 0 programming . programmable divider, div0, value and div0 reset bit. div0 can divide the input clock to the pcm or can be bypassed. 1 divider 1 programming . programmable divider, div1, value and div1 reset bit. div1 can divide the feedback clock input to the pcm or can be bypassed. valid only in pll mode. 2 divider 2 programming . programmable divider, div2, value and div2 reset bit. div2 can divide the output of the tapped delay line or can be bypassed and is only valid for the expressclk output. 3 dll 2x duty-cycle programming . dll mode clock doubler (2x) duty-cycle selection. 4 dll 1x duty-cycle programming . depending on the settings in other registers, this regis- ter is for: a. pll mode phase/delay selection; b. dll mode 1x duty cycle selection; and c. dll mode programmable delay. 5 mode programming . dll/pll mode selection, dll 1x/2x clock selection, phase detector feedback selection. 6 clock source status/output clock selection programming . input clock selection, feed- back clock selection, expressclk output source selection, system clock output source selec- tion. 7 pcm control programming . pcm power, reset, and con?uration control. select devices have been discontinued. see ordering information section for product status.
72 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) 5-5829(f) figure 46. pcm functional block diagram expressclk from programmable divider div0 register 7 register 6 register 5 register 4 register 3 register 2 register 1 register 0 fpga-pcm interface combinatorial logic programmable divider div2 0 1 2 3 s4 0 1 2 3 s10 0 system clock output expressclk output from expressclk feedback feedback clock programmable divider div1 0 1 s2 phase detector programmable delay lines (32 taps) charge pump and low-pass filter 1 0 s4 1...7 s5 1...7 1...7 1...7 s6 s7 s8 0 1 2 3 s4 0 1 2 3 s3 pcm input clock data_in[7:0] addr_in[2:0] data_out[7:0] we re lock pad routing 0 1 2 3 s0 routing select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 73 data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) delay-locked loop (dll) mode dll mode is used for implementing a delayed clock (phase adjustment), clock doubling, and duty cycle adjustment. all dll functions stem from a delay line with 32 taps. the delayed input clock is pulled from var- ious taps and processed to implement the desired result. there is no feedback clock in dll mode, provid- ing a very stable output and a fast lock time for the out- put clock. dll mode is selected by setting bit 0 in pcm register ?e to a 0. the settings for the various submodes of dll mode are described in the following paragraphs. divider div0 may be used with any of the dll modes to divide the input clock by an integer factor of 1 to 8 prior to implementation of the dll process. delayed clock a delayed version of the input clock can be constructed in dll mode. the output clock can be delayed by incre- ments of 1/32 of the input clock period. express clk and system clk outputs in delay modes are selected by setting register six, bits [5:4] to 10 or 11 for express- clk output, and/or bits [7:6] to 10 for system clock out- put. the delay value is entered in register four. see register four programming details for more information. delay values are also shown in the second column of table 27. note that when register six, bits [5:4] are set to 11, the expressclk output is divided by an integer factor from 1 to 8 while the system clock cannot be divided. the expressclk divider is provided so that the i/o clocking provided by the expressclk can operate slower than the internal system clock. this allows for very fast inter- nal processing while maintaining slower interface speeds off-chip for improved noise and power perfor- mance or to interoperate with slower devices in the sys- tem. the divisor of the expressclk frequency is selected in register two. see the register two program- ming details for more information. 1x clock duty-cycle adjustment a duty-cycle adjusted replica of the input clock can be constructed in dll mode. the duty cycle can be adjusted in 1/32 (3.125%) increments of the input clock period. dll 1x clock mode is selected by setting bit 4 of register ?e to a 1, and output clock source selection is selected by setting register six, bits [5:4] to 01 for expressclk output, and/or bits [7:6] to 01 for system clock output. the duty-cycle percentage value is entered in register four. see register four programming details for more information. duty cycle values are also shown in the third column of table 27. table 27. dll mode delay/1x duty cycle programming values register 4 [7:0] 7 6 5 4 3 2 1 0 delay (clk_in/32) duty cycle (% of clk_in) 0 0 x x x 0 0 0 1 3.125 0 0 x x x 0 0 1 2 6.250 0 0 x x x 0 1 0 3 9.375 0 0 x x x 0 1 1 4 12.500 0 0 x x x 1 0 0 5 15.625 0 0 x x x 1 0 1 6 18.750 0 0 x x x 1 1 0 7 21.875 0 0 x x x 1 1 1 8 25.000 0 1 x x x 0 0 0 9 28.125 0 1 x x x 0 0 1 10 31.250 0 1 x x x 0 1 0 11 34.375 0 1 x x x 0 1 1 12 37.500 0 1 x x x 1 0 0 13 40.625 0 1 x x x 1 0 1 14 43.750 0 1 x x x 1 1 0 15 46.875 0 1 1 1 1 x x x 16 50.000 1 0 0 0 0 x x x 17 53.125 1 0 0 0 1 x x x 18 56.250 1 0 0 1 0 x x x 19 59.375 1 0 0 1 1 x x x 20 62.500 1 0 1 0 0 x x x 21 65.625 1 0 1 0 1 x x x 22 68.750 1 0 1 1 0 x x x 23 71.875 1 0 1 1 1 x x x 24 75.000 1 1 0 0 0 x x x 25 78.125 1 1 0 0 1 x x x 26 81.250 1 1 0 1 0 x x x 27 84.375 1 1 0 1 1 x x x 28 87.500 1 1 1 0 0 x x x 29 90.625 1 1 1 0 1 x x x 30 93.750 1 1 1 1 0 x x x 31 96.875 select devices have been discontinued. see ordering information section for product status.
74 74 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) 2x clock duty-cycle adjustment a doubled-frequency, duty-cycle adjusted version of the input clock can be constructed in dll mode. the ?st clock cycle of the 2x clock output occurs when the input clock is high, and the second cycle occurs when the input clock is low. the duty cycle can be adjusted in 1/32 (6.25%) increments of the input clock period. additionally, each of the two doubled-clock cycles that occurs in a single input clock cycle may be adjusted to have different duty cycles. dll 2x clock mode is selected by setting bit 4 of register ?e to a 1, and by setting register six, bits [5:4] to 01 for expressclk out- put, and/or bits [7:6] to 01 for system clock output. the duty-cycle percentage value is entered in register three. see register three programming details for more information. duty-cycle values where both cycles of the doubled clock have the same duty cycle are also shown in table 28. table 28 . dll mode delay/2x duty cycle programming values phase-locked loop (pll) mode the pll mode of the pcm is used for clock multiplica- tion (1/8x to 64x) and clock delay minimization func- tions. pll functions make use of the pcm dividers and use feedback signals, often from the fpga array. the use of feedback is discussed with each pll submode. pll mode is selected by setting bit 0 of register ?e to 1. clock delay minimization pll mode can be used to minimize the effects of the input buffer and input routing delay on the clock signal. pll mode causes a feedback clock signal to align in phase with the input clock (refer back to the block dia- gram in figure 45) so that the delay between them is effectively eliminated. there is a dedicated feedback path from an adjacent middle clkcntrl block to the pcm . using the corner expressclk pad as the input to the pcm and using this dedicated feedback path, the clock from the express- clk output of the pcm , as viewed at the clkcntrl block, will be phase-aligned with the expressclk input to the pcm . these relationships are diagrammed in figure 47. a feedback clock can also be input to the pcm from general routing. this allows for compensating for delay between the pcm input and a point in the general rout- ing. the use of this routed-feedback path is not gener- ally recommended. because compensation is based on the programmable routing, the amount of clock delay compensation can vary between fpga lots and fabrication processes, and will vary each time that the feedback line is routed using different resources. con- tact lattice for application notes regarding the use of routed-feedback delay compensation. 5-5980(f) figure 47. expressclk delay minimization using the pcm register 3 [7:0] 7 6 5 4 3 2 1 0 duty cycle (%) 0 0 0 0 0 0 0 0 6.25 0 0 0 0 1 0 0 1 12.50 0 0 0 1 0 0 1 0 18.75 0 0 0 1 1 0 1 1 25.00 0 0 1 0 0 1 0 0 31.25 0 0 1 0 1 1 0 1 37.50 0 0 1 1 0 1 1 0 43.75 0 0 1 1 1 1 1 1 50.00 1 1 0 0 0 0 0 0 56.25 1 1 0 0 1 0 0 1 62.50 1 1 0 1 0 0 1 0 68.75 1 1 0 1 1 0 1 1 75.00 1 1 1 0 0 1 0 0 81.25 1 1 1 0 1 1 0 1 87.50 1 1 1 1 0 1 1 0 93.75 corner clkcntrl clkcntrl delay delay is compensated input output without using pcm output expressclk expressclk using pcm expressclk compensation equals delay select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 75 data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) clock multiplication an output clock that is a multiple (not necessarily an integer multiple) of the input clock can be generated in pll mode. the multiplication ratio is programmed in the division registers div0, div1, and div2. note that div2 applies only to the expressclk output of the pcm and any reference to div2 is implicitly 1 for the system clock output of the pcm . the clock multiplica- tion formulas when using expressclk feedback are: where the values of div0, div1, and div2 range from 1 to 8. the expressclk multiplication range of output clock frequencies is, therefore, from 1/8x up to 8x, with the system clock range up to 8x the expressclk frequency or 64x the input clock frequency. if system clock feed- back is used, the formulas are: the divider values, div0, div1, and div2 are pro- grammed in registers zero, one, and two, respectively. the multiplied output is selected by setting register six, bits [5:4] to 10 or 11 for expressclk output and/or bits [7:6] to 10 for system clock output. note that when reg- ister six, bits [5:4] are set to 11, the expressclk output is divided by div2, while the system clock cannot be divided. the expressclk divider is provided so that the i/o clocking provided by the expressclk can operate slower than the internal system clock. this allows for very fast internal processing while maintaining slower interface speeds off-chip for improved noise and power performance or to interoperate with slower devices in the system. it is also necessary to con?ure the internal pcm oscil- lator for operation in the proper frequency range. table 29 and table 30 show the settings required for register four for a given frequency range for series 3c and 3t devices. in addition, the acquisition time is shown for each frequency range. this is the time that is required for the pcm to acquire lock. the pcm oscil- lator frequency range is chosen based on the desired output frequency at the system clock output. if using the expressclk output, the equivalent system clock frequency can be selected by multiplying the expected expressclk output frequency by the value for div2. choose the nominal frequency from the table that is closest to the desired frequency, and use that value to program register four. minor adjustments to match the exact input frequency are then performed automatically by the pcm . f expressclk_out = f input_clock div1 div0 f system_clock_out = f expressclk_out div2 f system_clock_out = f input_clock ? div1 div0 f expressclk_out = f system_clock / div2 select devices have been discontinued. see ordering information section for product status.
76 76 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) table 29 . pcm oscillator frequency range 3txxx note: use of settings in the ?st three rows is not recommended. x means don? care. table 30 . pcm oscillator frequency range 3cxx note: use of settings in the ?st three rows is not recommended. x means don? care. register 4 76543210 min (mhz) system clock output frequency (mhz) nom max (mhz) t acquisition ( s) 00xxx010 17.00 58.50 100.00 36.00 00xxx011 16.10 52.50 89.00 37.00 00xxx100 15.17 49.00 82.80 38.00 00xxx101 14.25 45.00 76.50 39.00 00xxx110 13.33 41.50 70.30 40.00 00xxx111 12.40 38.00 64.00 41.00 01xxx000 12.20 36.75 61.30 43.75 01xxx001 12.10 35.00 58.00 46.50 01xxx010 11.90 33.00 54.30 49.25 01xxx011 11.70 31.30 51.00 52.00 01xxx100 11.10 30.00 49.40 54.75 01xxx101 10.50 29.15 47.80 57.50 01xxx110 10.00 28.10 46.20 60.25 01xxx111 9.40 27.00 44.60 63.00 10000xxx 9.20 26.25 43.30 65.40 10001xxx 9.00 25.65 42.30 67.80 10010xxx 8.80 25.00 41.30 70.10 10011xxx 8.60 24.45 40.30 72.50 10100xxx 8.40 23.70 39.00 74.90 10101xxx 8.10 22.90 37.70 77.30 10110xxx 7.90 22.20 36.50 79.60 10111xxx 7.70 21.50 35.20 82.00 11000xxx 7.60 20.80 34.00 84.30 11001xxx 7.45 20.10 32.80 86.50 11010xxx 7.30 19.45 31.60 88.80 11011xxx 7.20 18.85 30.50 91.00 11100xxx 6.60 18.30 30.00 93.30 11101xxx 6.00 17.70 29.40 95.50 11110xxx 5.50 17.10 28.60 97.80 11111xxx 5.00 16.50 28.00 100.00 register 4 76543210 min (mhz) system clock output frequency (mhz) nom max (mhz) t acquisition ( s) 00xxx010 10.50 73.00 135.00 36.00 00xxx011 10.00 68.00 126.00 37.00 00xxx100 9.50 63.00 117.00 38.00 00xxx101 9.10 58.50 108.00 39.00 00xxx110 8.60 53.80 99.00 40.00 00xxx111 8.10 49.00 90.00 41.00 01xxx000 7.80 47.70 87.50 43.80 01xxx001 7.60 46.30 85.00 46.50 01xxx010 7.30 45.00 82.50 49.30 01xxx011 7.10 43.60 80.00 52.00 01xxx100 6.80 42.10 77.50 55.00 01xxx101 6.50 40.75 75.00 57.50 01xxx110 6.30 39.40 72.50 60.30 01xxx111 6.00 38.00 70.00 63.00 10000xxx 5.90 37.40 68.80 65.40 10001xxx 5.90 36.70 67.50 67.80 10010xxx 5.80 36.00 66.30 70.10 10011xxx 5.80 35.40 65.00 72.50 10100xxx 5.70 35.00 63.80 74.90 10101xxx 5.60 34.10 62.50 77.30 10110xxx 5.60 33.50 61.30 79.60 10111xxx 5.50 32.80 60.00 82.00 11000xxx 5.40 32.10 58.80 84.30 11001xxx 5.40 31.50 57.50 86.50 11010xxx 5.30 30.70 56.30 88.80 11011xxx 5.30 30.10 55.00 91.00 11100xxx 5.20 29.50 53.80 93.30 11101xxx 5.10 28.80 52.50 95.50 11110xxx 5.10 28.20 51.30 97.80 11111xxx 5.00 27.50 50.00 100.00 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 77 data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) pcm/fpga internal interface writing and reading the pcm registers is done through a simple asynchronous interface that connects with the fpga routing resources. reads from the pcm by the fpga logic are accomplished by setting up the 3-bit address, a[2:0], and then applying an active-high read enable (re) pulse. the read data will be available as long as re is held high. the address may be changed while re is high, to read other addresses. when re goes low, the data output bus is 3-stated. writes to the pcm by the fpga logic are performed by applying the write data to the data input bus of the pcm , applying the 3-bit address to write to, and assert- ing the write enable (we) signal high. data will be writ- ten by the high-going transition of the we pulse. the read enable (re) and write enable (we) signals may not be active at the same time. for detailed timing information and speci?ations, see the timing charac- teristics section of this data sheet. the lock signal output from the pcm to the fpga routing indicates a stable output clock signal from the pcm . the lock signal is high when the pcm output clock parameters fall within the programmed values and the pcm speci?ations for jitter. due to phase cor- rections that occur internal to the pcm , the lock sig- nal might occasionally pulse low when the output clock is out of speci?ation for only one or two clock cycles (high jitter due to temperature, voltage ?ctuation, etc.) to accommodate these pulses, it is suggested that the user integrate the lock signal over a period suitable to their application to achieve the desired usage of the lock signal. the lock signal will also pulse high and low during the acquisition time as the output clock stabilizes. true lock is only achieved when the lock signal is a solid high. again, it is suggested that the user integrate the lock signal over a time period suitable to the subject application. pcm operation several features are available for the control of the pcm s overall operation. the pcm may be programma- bly enabled/disabled via bit 0 of register 7. when dis- abled, the analog power supply of the pcm is turned off, conserving power and eliminating the possibility of inducing noise into the system power buses. individual bits (register 7, bits [2:1]) are provided to reset the dll and pll functions of the pcm . these resets affect only the logic generating the dll or pll function; they do not reset the divider values (div0, div1, div2) or reg- isters [7:0]. the global set/reset (gsrn) is also pro- grammably controlled via register 7, bit 7. if register 7, bit 7 is set to 1, gsrn will have no effect on the pcm logic, allowing the clock to operate during a global set/reset. this function allows the fpga to be reset without affecting a clock that is sent off-chip and used elsewhere in the system. bit 6 of register 7 affects the functionality of the pcm during con?uration. if set to 1, this bit enables the pcm to operate during con?ura- tion, after the pcm has been con?ured. the pcm functionality is programmed via the bit stream. if regis- ter 7, bit 6 is 0, the pcm cannot function and its power supply is disabled until after the con?uration done signal goes high. when the pcm is powered up via register 7, bit 0, there is a wake-up time associated with its operation. follow- ing the wake-up time, the pcm will begin to fully func- tion, and, following an acquisition time during which the output clock may be unstable, the pcm will be in steady-state operation. there is also a shutdown time associated with powering off the pcm . the output clock will be unstable during this period. waveforms and tim- ing parameters can be found in the timing characteris- tics section of this data sheet. select devices have been discontinued. see ordering information section for product status.
78 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) pcm detailed programming descriptions of bit ?lds and individual control bits in the pcm control registers are provided in table 31. refer to figure 46 for more information on the location of the pcm elements that are discussed. in the following discussion, the duty cycle is in the percentage of the clock period where the clock is high. table 31 . pcm control registers bit # function register 0 divider 0 programming bits [3:0] 4-bit divider, div0, value . this value enables the input clock to immediately be divided by a value from 1 to 8. a 0 value (the default) indicates that div0 is bypassed (no division). bypass incurs less delay than dividing by 1. hexadecimal values greater than 8 for bits [3:0] yield their modulo 8 value. for example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1). bits [6:4] reserved . bit 7 div 0 reset bit . div0 may not be reset by gsrn depending on the value of register 7, bit 7. this bit may be set to 1 to reset div0 to its default value. bit 0 must be set to 0 (the default) to remove the reset. register 1 divider 1 programming bits [3:0] 4-bit divider, div1, value . this value enables the feedback clock to be divided by a value from 1 to 8. a 0 value (the default) indicates that div1 is bypassed (no division). bypass incurs less delay than dividing by 1. hexadecimal values greater than 8 for bits [3:0] yield their modulo 8 value. for example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1). bits [6:4] reserved . bit 7 div1 reset bit . div1 may not be reset by gsrn, depending on the value of register 7, bit 7. this bit may be set to 1 to reset div1 to its default value. bit 0 must be set to 0 (the default) to remove the reset. register 2 divider 2 programming bits [3:0] 4-bit divider, div2, value . this value enables the tapped delay line output clock driven onto expressclk to be divided by a value from 1 to 8. a 0 value (the default) indicates that div2 is bypassed (no division). bypass incurs less delay than dividing by 1. hexadecimal values greater than 8 for bits [3:0] yield their modulo 8 value. for example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1). bits [6:4] reserved . bit 7 div2 reset bit . div2 may not be reset by gsrn, depending on the value of register 7, bit 7. this bit may be set to 1 to reset div2 to its default value. bit 7 must be set to 0 (the default) to remove the reset. register 3 dll 2x duty-cycle programming bits [2:0] duty-cycle selection for the doubled clock period associated with the input clock high. the duty cycle is (value of bit 6) * 50% + ((value of bits [2:0]) + 1) * 6.25%. see the description for bit 6. bits [5:3] duty-cycle selection for the doubled clock period associated with the input clock low. the duty cycle is (value of bit 7) * 50% + ((value of bits [2:0]) + 1) * 6.25%. see the description for bit 7. bit 6 master duty-cycle control for the ?st clock period of the doubled clock: 0 = less than or equal to 50%, 1 = greater than 50%. bit 7 master duty-cycle control for the second clock period of the doubled clock: 0 = less than or equal to 50%, 1 = greater than 50%. example: both clock periods having a 62.5% duty cycle, bits [7:0] are 11 001 001. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 79 data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) table 31. pcm control registers (continued) bit # function register 4 dll 1x duty-cycle programming bits [2:0] duty-cycle/delay selection for duty cycle/delays less than or equal to 50% . the duty- cycle/delay is (value of bits [7:6]) * 25% + ((value of bits [2:0]) + 1) * 3.125%. see the description for bits [7:6]. bits [5:3] duty-cycle/delay selection for duty cycle/delays greater than 50% . the duty-cycle/delay is (value of bits [7:6]) * 25% + ((value of bits [5:3]) + 1) * 3.125%. see the description for bits [7:6]. bits [7:6] master duty cycle control: 00: duty cycle 3.125% to 25% 01: duty cycle 28.125% to 50% 10: duty cycle 53.125% to 75% 11: duty cycle 78.125% to 96.875% example: a 40.625% duty cycle, bits [7:0] are 01 xxx 100, where x is a don? care because the duty cycle is not greater than 50%. example: the pcm output clock should be delayed 96.875% (31/32) of the input clock period. bits [7:0] are 11110xxx, which is 78.125% from bits [7:6] and 18.75% from bits [5:3]. bits [2:0] are don? care (x) because the delay is greater than 50%. register 5 mode programming bit 0 dll/pll mode selection bit . 0 = dll, 1 = pll. default is dll mode. bit 1 reserved . bit 2 pll phase detector feedback input selection bit . 0 = feedback signal from routing/ expressclk , 1 = feedback from programmable delay line output. default is 0. has no effect in dll mode. bit 3 reserved . bit 4 1x/2x clock selection bit for dll mode . 0 = 1x clock output, 1 = 2x clock output. default is 1x clock output. has no effect in pll mode. bits [7:5] reserved . select devices have been discontinued. see ordering information section for product status.
80 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) table 31. pcm control registers (continued) bit # function bits [5:4] expressclk output source selector . default is 00. 00: pcm input clock, bypass path through pcm 01: dll output 10: tapped delay line output 11: divided (div2) delay line output bits [7:6] system clock output source selector . default is 00. 00: pcm input clock, bypass path through pcm 01: dll output 10: tapped delay line output 11: reserved register 7 pcm control programming bit 0 pcm analog power supply switch . 1 = power supply on, 0 = power supply off. bit 1 pcm reset . a value of 1 resets all pcm logic for pll and dll modes. bit 2 dll reset . a value of 1 resets the clock generation logic for dll mode. no dividers or user reg- isters are affected. bits [5:3] reserved . bit 6 pcm configuration operation enable bit . 0 = normal con?uration operation. during con?u- ration (done = 0), the pcm analog power supply will be off, the pcm output data bus is 3-stated, and the lock signal is asserted to logic 0. the pcm will power up when done = 1. 1 = pcm operation during con?uration. the pcm may be powered up (see bit 0) and begin operation, or continue operation. the setup of the pcm can be performed via the con?uration bit stream. bit 7 pcm gsrn enable bit . 0 = normal gsrn operation. 1 = gsrn has no effect on pcm logic, so clock processing will not be interrupted by a chip reset. default is 0. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 81 data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) pcm applications the applications discussed below are only a small sampling of the possible uses for the pcm . check the lattice website for additional application notes. clock phase adjustment the pcm may be used to adjust the phase of the input clock. the result is an output clock which has its active edge either preceding or following the active edge of the input clock. clock phase adjustment is accom- plished in dll mode by delaying the clock. this is dis- cussed in the delay-locked loop (dll) mode section. examples of using the delayed clock as an early or late phase-adjusted clock are outlined in the following para- graphs. an output clock that precedes the input clock can be used to compensate for clock delay that is largely due to excessive loading. the preceding output clock is really not early relative to the input clock, but is delayed almost a full cycle. this is shown in figure 48a. the amount of delay that is being compensated for, plus clock setup time and some margin, is the amount less than one full clock cycle that the output clock is delayed from the input clock. in some systems, it is desirable to operate logic from several clocks that operate at different phases. this technique is often used in microprocessor-based sys- tems to transfer and process data synchronously between functional areas, but without incurring exces- sive delays. figure 48b shows an input clock and an output clock operating 180?out of phase. it also shows a version of the input clock that was shifted approxi- mately 180?using logic gates to create an inverter. note that the inverted clock is really shifted more than 180?due to the propagation delay of the inverter. the pcm output clock does not suffer from this delay. addi- tionally, the 180?shifted pcm output could be shifted by some smaller amount to effect an early 180?shifted clock that also accounts for loading effects. in terms of degrees of phase shift, the phase of a clock is adjustable in dll mode with resolution relative to the delay increment (see table 27): phase adjustment = (delay)* 11.25, delay < 16 phase adjustment = ((delay)* 11.25) ?360, delay > 16 5-5979(f) figure 48. clock phase adjustment using the pcm input clock output clock input clock pcm output clock inverted input clock a. generating an early clock b. multiphase clock generation using the dll unintended phase shift due to inverter delay dll delay dll delay clock delay and setup being compensated select devices have been discontinued. see ordering information section for product status.
82 82 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) high-speed internal processing with slow i/os the pcm pll mode provides two outputs, one sent to the global system clock routing of the fpga and the other to the expressclk (s) that serve the fpga i/os. the expressclk output of the pcm has a divide capa- bility (div2) that the system clock output does not. this feature allows an input clock to be multiplied up to a higher frequency for high-speed internal processing, and also allows the expressclk output to be divided down to a lower frequency to accommodate off-fpga data transfers. for example, a 10 mhz input clock may be multiplied (see clock multiplication in the phase- locked loop (pll) mode subsection) to 25 mhz (div0 = 4, div1 = 5, div2 = 2) and output to the fpga expressclk . this allows the i/os of the circuit to run at 25 mhz ((2 * 5)/4 * 10 mhz). the system clock will run at div2 times the expressclk rate, which is 2 times 25 mhz, or 50 mhz. this setup allows for internal pro- cessing to occur at twice the rate of on/off device i/o transfers. pcm cautions cautions do apply when using the pcm . there are a number of con?urations that are possible in the pcm that are theoretically valid, but may not produce viable results. this section describes some of those situa- tions, and should leave the user with an understanding of the types of pitfalls that must be avoided when modi- fying clock signals. resultant signals from the pcm must meet the fpga timing speci?ations. it is possible to specify pulses by using duty-cycle adjustments that are too narrow to function in the fpga. for instance, if a 40 mhz clock is doubled to 80 mhz and a 6.25% duty cycle is selected, the result will be a 780 ps pulse that repeats every 12.5 ns. this pulse falls outside of the clock pulse width speci?ation and is not valid. using divider div2, it is possible to specify a clock mul- tiplication factor of 64 between the input clock and the output system clock. as mentioned above, the resultant frequency must meet all fpga timing speci?ations. the input clock must also meet the minimum speci?a- tions. an input clock rate that is below the pcm clock minimum cannot be used even if the multiplied output is within the allowable range. the use of the pcm to tweak a clock signal to eliminate a particular problem, such as a single setup time viola- tion, is discouraged. a small shift in delay, duty cycle, or phase to correct a single-point problem is in essence an asynchronous patch to a synchronous system, mak- ing the system less stable. this type of local problem, as opposed to a global clock control issue like device- wide clock delay, can usually be eliminated through more robust design practices. if this type of change is made, the designer must be aware that depending on the extent of the change made, the design may fail to operate correctly in a different speed grade or voltage grade (e.g., 3c vs. 3t), or even in a different production lot of the same device. divider div2 is available in dll mode for the express- clk output, but its use is not recommended with duty- cycle adjusted clocks. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 83 data sheet november 2006 orca series 3c and 3t fpgas fpga states of operation prior to becoming operational, the fpga goes through a sequence of states, including initialization, con?ura- tion, and start-up. figure 49 outlines these three fpga states. figure 49. fpga states of operation initialization upon powerup, the device goes through an initialization process. first, an internal power-on-reset circuit is trig- gered when power is applied. when v dd reaches the voltage at which portions of the fpga begin to operate (2.5 v to 3 v for the or3cxx, 2.2 v to 2.7 v for the or3txxx), the i/os are con?ured based on the con- ?uration mode, as determined by the mode select inputs m[2:0]. a time-out delay is initiated when v dd reaches between 3.0 v and 4.0 v (or3cxx) or 2.7 v to 3.0 v (or3txxx) to allow the power supply voltage to stabilize. the init and done outputs are low. at pow- erup, if v dd does not rise from 2.0 v to v dd in less than 25 ms, the user should delay con?uration by inputting a low into init , prgm , or reset until v dd is greater than the recommended minimum operating voltage (4.75 v for or3cxx commercial devices and 3.0 v for or3txxx devices). at the end of initialization, the default con?uration option is that the con?uration ram is written to a low state. this prevents shorts prior to con?uration. as a con?uration option, after the ?st con?uration (i.e., at recon?uration), the user can recon?ure without clearing the internal con?uration ram ?st. the active-low, open-drain initialization signal init is released and must be pulled high by an external resis- tor when initialization is complete. to synchronize the con?uration of multiple fpgas, one or more init pins should be wire-anded. if init is held low by one or more fpgas or an external device, the fpga remains in the initialization state. init can be used to signal that the fpgas are not yet initialized. after init goes high for two internal clock cycles, the mode lines (m[3:0]) are sampled, and the fpga enters the con?uration state. the high during con?uration (hdc), low during con?- uration ( ldc ), and done signals are active outputs in the fpgas initialization and con?uration states. hdc, ldc , and done can be used to provide control of external logic signals such as reset, bus enable, or prom enable during con?uration. for parallel master con?uration modes, these signals provide prom enable control and allow the data pins to be shared with user logic signals. 5-4529(f) ?active i/o ?release internal reset ?done goes high start-up initialization configuration reset or prgm low prgm low ?clear configuration ?init low, hdc high, ldc low operation powerup ?power-on time delay ?m[3:0] mode is selected ?configuration data frame ?init high, hdc high, ldc low ?dout active yes no no reset , init , or prgm low bit error yes written memory select devices have been discontinued. see ordering information section for product status.
84 84 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas fpga states of operation (continued) if con?uration has begun, an assertion of reset or prgm initiates an abort, returning the fpga to the ini- tialization state. the prgm and reset pins must be pulled back high before the fpga will enter the con?- uration state. during the start-up and operating states, only the assertion of prgm causes a recon?uration. in the master con?uration modes, the fpga is the source of con?uration clock (cclk). in this mode, the initialization state is extended to ensure that, in daisy- chain operation, all daisy-chained slave devices are ready. independent of differences in clock rates, master mode devices remain in the initialization state an addi- tional six internal clock cycles after init goes high. when con?uration is initiated, a counter in the fpga is set to 0 and begins to count con?uration clock cycles applied to the fpga. as each con?uration data frame is supplied to the fpga, it is internally assem- bled into data words. each data word is loaded into the internal con?uration memory. the con?uration load- ing process is complete when the internal length count equals the loaded length count in the length count ?ld, and the required end of con?uration frame is written. all or3cxx i/os operate as ttl inputs during con?u- ration (or3txxx i/os are cmos-only). all i/os that are not used during the con?uration process are 3-stated with internal pull-ups. warning : during con?uration, all or3txxx inputs have internal pull-ups enabled. if these inputs are driven to 5v, they will draw substantial current ( ? 5 ma). this is due to the fact that the inputs are pulled up to 3v. during con?uration, the pic and plc latches/ffs are held set/reset and the internal bidi buffers are 3- stated. the combinatorial logic begins to function as the fpga is con?ured. figure 50 shows the general waveform of the initialization, con?uration, and start- up states. con?uration the orca series fpga functionality is determined by the state of internal con?uration ram. this con?ura- tion ram can be loaded in a number of different modes. in these con?uration modes, the fpga can act as a master or a slave of other devices in the sys- tem. the decision as to which con?uration mode to use is a system design issue. con?uration is dis- cussed in detail, including the con?uration data format and the con?uration modes used to load the con?u- ration data in the fpga, following a description of the start-up state. 5-4482(f) figure 50. initialization/configuration/start-up waveforms v dd m[3:0] cclk hdc ldc done user i/o internal reset (gsrn) configuration operation initialization start-up reset prgm init select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 85 data sheet november 2006 orca series 3c and 3t fpgas fpga states of operation (continued) start-up after con?uration, the fpga enters the start-up phase. this phase is the transition between the con?- uration and operational states and begins when the number of cclks received after init goes high is equal to the value of the length count ?ld in the con?- uration frame and when the end of con?uration frame has been written. the system design issue in the start- up phase is to ensure the user i/os become active without inadvertently activating devices in the system or causing bus contention. a second system design concern is the timing of the release of global set/reset of the plc latches/ffs. there are con?uration options that control the relative timing of three events: done going high, release of the set/reset of internal ffs, and user i/os becoming active. figure 51 shows the start-up timing for orca fpgas. the system designer determines the relative timing of the i/os becoming active, done going high, and the release of the set/reset of internal ffs. in the orca series fpga, the three events can occur in any arbitrary sequence. this means that they can occur before or after each other, or they can occur simulta- neously. there are four main start-up modes: cclk_nosync, cclk_sync, uclk_nosync, and uclk_sync. the only difference between the modes starting with cclk and those starting with uclk is that for the uclk modes, a user clock must be supplied to the start-up logic. the timing of start-up events is then based upon this user clock, rather than cclk. the dif- ference between the sync and nosync modes is that for sync mode, the timing of two of the start-up events, release of the set/reset of internal ffs, and the i/os becoming active is triggered by the rise of the external done pin followed by a variable number of rising clock edges (either cclk or uclk). for the nosync mode, the timing of these two events is based only on either cclk or uclk. done is an open-drain bidirectional pin that may include an optional (enabled by default) pull-up resistor to accommodate wired anding. the open-drain done signals from multiple fpgas can be tied together (anded) with a pull-up (internal or external) and used as an active-high ready signal, an active-low prom enable, or a reset to other portions of the system. when used in sync mode, these anded done pins can be used to synchronize the other two start-up events, since they can all be synchronized to the same external signal. this signal will not rise until all fpgas release their done pins, allowing the signal to be pulled high. the default for orca is the cclk_sync synchro- nized start-up mode where done is released on the ?st cclk rising edge, c1 (see figure 51). since this is a synchronized start-up mode, the open-drain done signal can be held low externally to stop the occurrence of the other two start-up events. once the done pin has been released and pulled up to a high level, the other two start-up events can be programmed individu- ally to either happen immediately or after up to four ris- ing edges of cclk (di, di + 1, di + 2, di + 3, di + 4). the default is for both events to happen immediately after done is released and pulled high. a commonly used design technique is to release done one or more clock cycles before allowing the i/o to become active. this allows other con?uration devices, such as proms, to be disconnected using the done signal so that there is no bus contention when the i/os become active. in addition to controlling the fpga during start-up, other start-up techniques that avoid contention include using isolation devices between the fpga and other circuits in the system, reassigning i/o locations, and maintaining i/os as 3- stated outputs until contentions are resolved. each of these start-up options can be selected during bit stream generation in isplever, using advanced options. for more information, please see the isplever documentation. select devices have been discontinued. see ordering information section for product status.
86 86 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas fpga states of operation (continued) note: f = ?ished, no more clks required. 5-2761(f) figure 51. start-up waveforms reconguration to recon?ure the fpga when the device is operating in the system, a low pulse is input into prgm . the con- ?uration data in the fpga is cleared, and the i/os not used for con?uration are 3-stated. the fpga then samples the mode select inputs and begins recon?u- ration. when recon?uration is complete, done is released, allowing it to be pulled high. partial reconguration all orca device families have been designed to allow a partial recon?uration of the fpga at any time. this is done by setting a bit stream option in the previous con?uration sequence that tells the fpga to not reset all of the con?uration ram during a recon?uration. then only the con?uration frames that are to be modi- ?d need to be rewritten, thereby reducing the con?u- ration time. other bit stream options are also available that allow one portion of the fpga to remain in operation while a partial recon?uration is being done. if this is done, the user must be careful to not cause contention between the two con?urations (the bit stream resident in the fpga and the partial recon?uration bit stream) as the second recon?uration bit stream is being loaded. other conguration options there are many other con?uration options available to the user that can be set during bit stream generation in isplever. these include options to enable boundary scan and/or the microprocessor interface ( mpi ) and/or the programmable clock manager ( pcm ), readback options, and options to control and use the internal oscillator after con?uration. other useful options that affect the next con?uration (not the current con?uration process) include options to disable the global set/reset during con?uration, dis- able the 3-state of i/os during con?uration, and dis- able the reset of internal rams during con?uration to allow for partial con?urations (see above). for more information on how to set these and other con?uration options, please see the isplever documentation. di c1 c2 c3 c4 f c1 c2 c3 c4 c1 c2 c3 c4 c1, c2, c3, or c4 di + 1di di + 2 di + 3 di + 4 di + 1di di + 2 di + 3 di + 4 cclk_sync done in u1 u2 u3 u4 f u1 u2 u3 u4 u1 u2 u3 u4 uclk_nosync di + 1di di + 2 di + 3 di + 4 di + 1 di + 2 di + 3 uclk_sync uclk period synchronization uncertainty done in f c1 c1 u1, u2, u3, or u4 done i/o gsrn active done i/o gsrn active done i/o gsrn active done i/o gsrn active uclk f cclk_nosync select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 87 data sheet november 2006 orca series 3c and 3t fpgas con?uration data format the isplever development system interfaces with front-end design entry tools and provides tools to pro- duce a fully con?ured fpga. this section discusses using the isplever development system to generate con?uration ram data and then provides the details of the con?uration frame format. the orca or3cxx and or3txxx series fpgas are bit stream compatible. using isplever to generate con?uration ram data the con?uration data bit stream de?es the i/o func- tionality, logic, and interconnections within the fpga. the bit stream is generated by the development sys- tem. the bit stream created by the bit stream genera- tion tool is a series of 1s and 0s used to write the fpga con?uration ram. it can be loaded into the fpga using one of the con?uration modes discussed later. in the bit stream generator, the designer selects options that affect the fpgas functionality. using the output of the bit stream generator, circuit_name.bit , the development systems download tool can load the con?uration data into the orca series fpga evalua- tion board from a pc or workstation. alternatively, a user can program a prom (such as a serial rom or a standard eprom) and load the fpga from the prom. the development systems prom programming tool produces a ?e in .mks or .exo for- mat. con?uration data frame con?uration data can be presented to the fpga in two frame formats: autoincrement and explicit. a detailed description of the frame formats is shown in figure 52, figure 53, and table 32. the two modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream size, and explicit mode requires an address for each data frame. in both cases, the header frame begins with a series of 1s and a preamble of 0010, followed by a 24-bit length count ?ld representing the total number of con?uration clocks needed to complete the loading of the fpgas. following the header frame is a mandatory id frame. (note that the id frame was optional in the orca 2c and 2c/txxa series.) the id frame contains data used to determine if the bit stream is being loaded to the correct type of orca fpga (i.e., a bit stream generated for an or3t55 is being sent to an or3t55). error checking is always enabled for series 3 devices, through the use of an 8-bit checksum. one bit in the id frame also selects between the autoincrement and explicit address modes for this load of the con?uration data. a con?uration data frame follows the id frame. a data frame starts with a 01-start bit pair and ends with enough 1-stop bits to reach a byte boundary. if using autoincrement con?uration mode, subsequent data frames can follow. if using explicit mode, one or more address frames must follow each data frame, telling the fpga at what addresses the preceding data frame is to be stored (each data frame can be sent to multiple addresses). following all data and address frames is the postam- ble. the format of the postamble is the same as an address frame with the highest possible address value with the checksum set to all ones. select devices have been discontinued. see ordering information section for product status.
88 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas con?uration data format (continued) 5-5759(f) figure 52. serial con?uration data format?utoincrement mode 5-5760(f) figure 53. serial con?uration data format?xplicit mode table 32. configuration frame format and contents * in mpi con?uration mode, the number of stop bits = 32. note: for slave parallel mode, the byte containing the preamble must be 11110010. the number of leading header dummy bits must be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive integer. the number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. note also that the bit stream generator tool supplies a bit stream that is compatible with all con?uration modes, including slave parallel mode. header 11110010 preamble 24-bit length count con?uration frame length. 11111111 trailing header? bits. id frame 0101 1111 1111 1111 id frame header. con?uration mode 00 = autoincrement, 01 = explicit. reserved [41:0] reserved bits set to 0. id 20-bit part id. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. configuration data frame (repeated for each data frame) 01 data frame header. data bits number of data bits depends upon device. alignment bits = 0 string of 0 bits added to bit stream to make frame header, plus data bits reach a byte boundary. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. configuration address frame 00 address frame header. 14 address bits 14-bit address of location to start data storage. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. postamble 00 postamble header. 11111111 111111 dummy address. 1111111111111111 16 stop bits.* configuration data configuration data 10 01 01 preamble length id frame configuration configuration postamble configuration header 00 00 count data frame 1 data frame 2 preamble length id frame configuration configuration postamble configuration header address address 00 count data frame 1 data frame 2 frame 2 frame 1 configuration data configuration data 10 01 01 00 00 00 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 89 data sheet november 2006 orca series 3c and 3t fpgas con?uration data format (continued) the length and number of data frames and information on the prom size for the series 3 fpgas are given in table 33. table 33. configuration frame size bit stream error checking there are three different types of bit stream error checking performed in the orca series 3 fpgas: id frame, frame alignment, and crc checking. the id data frame is sent to a dedicated location in the fpga. this id frame contains a unique code for the device for which it was generated. this device code is compared to the internal code of the fpga. any differences are ?gged as an id error. this frame is automatically created by the bit stream generation program in isplever. each data and address frame in the fpga begins with a frame start pair of bits and ends with eight stop bits set to 1. if any of the previous stop bits were a 0 when a frame start pair is encountered, it is ?gged as a frame align- ment error. error checking is also done on the fpga for each frame by means of a checksum byte. if an error is found on eval- uation of the checksum byte, then a checksum/parity error is ?gged. the checksum is the xor of all the data bytes, from the start of frame up to and including the bytes before the checksum. it applies to the id, address, and data frames. when any of the three possible errors occur, the fpga is forced into an idle state, forcing init low. the fpga will remain in this state until either the reset or prgm pins are asserted. if using either of the mpi modes to con?ure the fpga, the speci? type of bit stream error is written to one of the mpi registers by the fpga con?uration logic. the pgrm bit of the mpi control register can also be used to reset out of the error condition and restart con?uration. devices or3t20 or3t30 or3t55 or3c/t80 or3t125 # of frames 856 984 1240 1496 1880 data bits/frame 202 232 292 352 442 con?uration data (# of frames x # of data bits/frame) 172,912 228,288 362,080 526,592 830,960 maximum total # bits/frame (align bits, 01 frame start, 8-bit checksum, 8 stop bits) 224 256 312 376 464 maximum con?uration data (# bits/frame x # of frames) 191,744 251,904 386,880 562,496 872,320 maximum prom size (bits) (add con?uration header and postamble) 191,912 252,072 387,048 562,664 872,488 select devices have been discontinued. see ordering information section for product status.
90 90 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas fpga con?uration modes there are eight methods for con?uring the fpga. seven of the con?uration modes are selected on the m0, m1, and m2 inputs. the eighth con?uration mode is accessed through the boundary-scan interface. a fourth input, m3, is used to select the frequency of the internal oscillator, which is the source for cclk in some con?uration modes. the nominal frequencies of the internal oscillator are 1.25 mhz and 10 mhz. the 1.25 mhz frequency is selected when the m3 input is unconnected or driven to a high state. there are three basic fpga con?uration modes: master, slave, and peripheral. the con?uration data can be transmitted to the fpga serially or in parallel bytes. as a master, the fpga provides the control sig- nals out to strobe data in. as a slave device, a clock is generated externally and provided into the cclk input. in the three peripheral modes, the fpga acts as a microprocessor peripheral. table 34 lists the functions of the con?uration mode pins. note that two con?ura- tion modes previously available on the or2cxx and or2c/txxa devices (master parallel down and syn- chronous peripheral) have been removed for series 3 devices. table 34. configuration modes * motorola is a registered trademark of motorola, inc. master parallel mode the master parallel con?uration mode is generally used to interface to industry-standard, byte-wide mem- ory, such as the 2764 and larger eproms. figure 54 provides the connections for master parallel mode. the fpga outputs an 18-bit address on a[17:0] to memory and reads 1 byte of con?uration data on the rising edge of rclk. the parallel bytes are internally serial- ized starting with the least signi?ant bit, d0. d[7:0] of the fpga can be connected to d[7:0] of the micropro- cessor only if a standard prom ?e format is used. if a .bit or .rbt ?e is used from isplever, then the user must mirror the bytes in the .bit or .rbt ?e or leave the .bit or .rbt ?e unchanged and connect d[7:0] of the fpga to d[0:7] of the microprocessor. figure 54. master parallel con?uration schematic in master parallel mode, the starting memory address is 00000 hex, and the fpga increments the address for each byte loaded. one master mode fpga can interface to the memory and provide con?uration data on dout to additional fpgas in a daisy-chain. the con?uration data on dout is provided synchronously with the falling edge of cclk. the frequency of the cclk output is eight times that of rclk. m2 m1 m0 cclk configuration mode data 0 0 0 output master serial serial 0 0 1 input slave parallel parallel 0 1 0 output microprocessor: motorola * pow- erpc parallel 0 1 1 output microprocessor: intel i960 parallel 1 0 0 output master parallel parallel 1 0 1 output async peripheral parallel 1 1 0 reserved 1 1 1 input slave serial serial eprom a[17:0] done m2 m1 m0 hdc orca series fpga rclk ldc v dd d[7:0] dout cclk to daisy- chained devices v dd or gnd prgm program a[17:0] d[7:0] oe ce select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 91 data sheet november 2006 orca series 3c and 3t fpgas fpga con?uration modes (continued) master serial mode in the master serial mode, the fpga loads the con?u- ration data from an external serial rom. the con?ura- tion data is either loaded automatically at start-up or on a prgm command to recon?ure. the att1700a series serial proms can be used to con?ure the fpga in the master serial mode. this provides a sim- ple 4-pin interface in a compact package. con?uration in the master serial mode can be done at powerup and/or upon a con?ure command. the sys- tem or the fpga must activate the serial rom's reset /oe and ce inputs. at powerup, the fpga and serial rom each contain internal power-on reset cir- cuitry that allows the fpga to be con?ured without the system providing an external signal. the power-on reset circuitry causes the serial rom's internal address pointer to be reset. after powerup, the fpga automati- cally enters its initialization phase. the serial rom/fpga interface used depends on such factors as the availability of a system reset pulse, avail- ability of an intelligent host to generate a con?ure command, whether a single serial rom is used or mul- tiple serial roms are cascaded, whether the serial rom contains a single or multiple con?uration pro- grams, etc. because of differing system requirements and capabilities, a single fpga/serial rom interface is generally not appropriate for all applications. data is read in the fpga sequentially from the serial rom. the data output from the serial rom is con- nected directly into the din input of the fpga. the cclk output from the fpga is connected to the clk input of the serial rom. during the con?uration pro- cess, cclk clocks one data bit on each rising edge. since the data and clock are direct connects, the fpga/serial rom design task is to use the system or fpga to enable the reset /oe and ce of the serial rom(s). there are several methods for enabling the serial roms reset /oe and ce inputs. the serial roms reset /oe is programmable to function with reset active-high and oe active-low or reset active- low and oe active-high. in figure 55, serial roms are cascaded to con?ure multiple daisy-chained fpgas. the host generates a 500 ns low pulse into the fpga's prgm input. the fpgas init input is connected to the serial roms reset /oe input, which has been programmed to function with reset active-low and oe active-high. the fpga done is routed to the ce pin. the low on done enables the serial roms. at the completion of con?uration, the high on the fpga's done disables the serial rom. serial roms can also be cascaded to support the con- ?uration of multiple fpgas or to load a single fpga when con?uration data requirements exceed the capacity of a single serial rom. after the last bit from the ?st serial rom is read, the serial rom outputs ceo low and 3-states the data output. the next serial rom recognizes the low on ce input and outputs con- ?uration data on the data output. after con?uration is complete, the fpgas done output into ce disables the serial roms. this fpga/serial rom interface is not used in applica- tions in which a serial rom stores multiple con?ura- tion programs. in these applications, the next con?uration program to be loaded is stored at the rom location that follows the last address for the previ- ous con?uration program. the reason the interface in figure 55 will not work in this application is that the low output on the init signal would reset the serial rom address pointer, causing the ?st con?uration to be reloaded. in some applications, there can be contention on the fpga's din pin. during con?uration, din receives con?uration data, and after con?uration, it is a user i/o. if there is contention, an early done at start-up (selected in isplever) may correct the problem. an alternative is to use ldc to drive the serial rom's ce pin. in order to reduce noise, it is generally better to run the master serial con?uration at 1.25 mhz (m3 pin tied high), rather than 10 mhz, if possible. figure 55. master serial con?uration schematic att1700a din m2 m1 m0 orca series fpga cclk dout to daisy- chained devices data clk ce ceo att1700a data clk reset /oe ceo ce to more serial roms as needed done init pr ogram reset /oe prgm 5-4456.1(f) select devices have been discontinued. see ordering information section for product status.
92 92 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas fpga con?uration modes (continued) asynchronous peripheral mode figure 56 shows the connections needed for the asyn- chronous peripheral mode. in this mode, the fpga system interface is similar to that of a microprocessor- peripheral interface. the microprocessor generates the control signals to write an 8-bit byte into the fpga. the fpga control inputs include active-low cs0 and active- high cs1 chip selects and wr and rd inputs. the chip selects can be cycled or maintained at a static level during the con?uration cycle. each byte of data is writ- ten into the fpgas d[7:0] input pins. d[7:0] of the fpga can be connected to d[7:0] of the microproces- sor only if a standard prom ?e format is used. if a .bit or .rbt ?e is used from isplever, then the user must mirror the bytes in the .bit or .rbt ?e or leave the .bit or .rbt ?e unchanged and connect d[7:0] of the fpga to d[0:7] of the microprocessor. the fpga provides an rdy/ b usy status output to indi- cate that another byte can be loaded. a low on rdy/ b usy indicates that the double-buffered hold/shift reg- isters are not ready to receive data, and this pin must be monitored to go high before another byte of data can be written. the shortest time rdy/ b usy is low occurs when a byte is loaded into the hold register and the shift register is empty, in which case the byte is immediately transferred to the shift register. the long- est time for rdy/ b usy to remain low occurs when a byte is loaded into the holding register and the shift register has just started shifting con?uration data into con?uration ram. the rdy/ b usy status is also available on the d7 pin by enabling the chip selects, setting wr high, and apply- ing rd low, where the rd input provides an output enable for the d7 pin when rd is low. the d[6:0] pins are not enabled to drive when rd is low and, therefore, only act as input pins in asynchronous peripheral mode. optionally, the user can ignore the rdy/ b usy status and simply wait until the maximum time it would take for the rdy/ b usy line to go high, indicating the fpga is ready for more data, before writing the next data byte. figure 56. asynchronous peripheral con?uration microprocessor interface (mpi) mode the built-in mpi in series 3 fpgas is designed for use in con?uring the fpga. figure 57 and figure 58 show the glueless interface for fpga con?uration and read- back from the powerpc and i960 processors, respec- tively. when enabled by the mode pins, the mpi handles all con?uration/readback control and hand- shaking with the host processor. for single fpga con- ?uration, the host sets the con?uration control register prgm bit to zero then back to a one and, after reading that the init signal is high in the mpi status register, transfers data 8 bits at a time to the fpgas d[7:0] input pins. if con?uring multiple fpgas through daisy-chain operation is desired, the mp_daisy bit must be set in the con?uration control register of the mpi . because of the latency involved in a daisy-chain con?uration, the mp_hold_bus bit may be set to zero rather than one for daisy-chain operation. this allows the mpi to acknowledge the data transfer before the con?uration information has been serialized and transferred on the fpga daisy-chain. the early acknowledgment frees the host processor to perform other system tasks. con- ?uring with the mp_hold_bus bit at zero requires that the host microprocessor poll the rdy/ b usy bit of the mpi status register and/or use the mpi interrupt capability to con?m the readiness of the mpi for more con?uration data. micro- processor d[7:0] cs1 m2 m1 m0 hdc orca series fpga 8 ldc v dd done cs0 dout cclk to daisy- chained devices bus controller address decode logic rd wr rdy/busy init prgm select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 93 data sheet november 2006 orca series 3c and 3t fpgas fpga con?uration modes (continued) there are two options for using the host interrupt request in con?uration mode. the con?uration con- trol register offers control bits to enable the interrupt on either a bit stream error or to notify the host processor when the fpga is ready for more con?uration data. the mpi status register may be used in conjunction with, or in place of, the interrupt request options. the status register contains a 2-bit ?ld to indicate the bit stream error status. as previously mentioned, there is also a bit to indicate the mpi s readiness to receive another byte of con?uration data. a ?w chart of the mpi con?uration process is shown in figure 59. the mpi status and con?uration register bit maps can be found in the special function blocks section and mpi con?uration timing information is available in the tim- ing characteristics section of this data sheet. 5-5761(f) note: fpga shown as a memory-mapped peripheral using cs0 and cs1. other decoding schemes are possible using cs0 and/or cs1. figure 57. powerpc /mpi con?uration schematic 5-5762(f) note: fpga shown as only system peripheral with ?ed chip select signals. for multiperipheral systems, address decoding and/or latching can be used to implement chip selects. figure 58. i960 /mpi con?uration schematic con?uration readback can also be performed via the mpi when it is in user mode. the mpi is enabled in user mode by setting the mp_user bit to 1 in the con?ura- tion control register prior to the start of con?uration or through a con?uration option. to perform readback, the host processor writes the 14-bit readback start address to the readback address registers and sets the rd_cfg bit to 0 in the con?uration control register. readback data is returned 8 bits at a time to the read- back data register and is valid when the data_rdy bit of the status register is 1. there is no error checking during readback. a ?w chart of the mpi readback operation is shown in figure 60. the rd_data pin used for dedicated fpga readback is invalid during mpi readback. 5-5763(f) figure 59. con?uration through mpi dout cclk d[7:0] a[4:0] mpi_clk mpi_rw mpi_ack mpi_bi mpi_irq mpi_strb cs0 cs1 hdc ldc d[7:0] a[27:31] clkout rd/wr ta bi irq x ts a26 a25 to daisy- chained devices powerpc orca 8 fpga series 3 done init dout cclk d[7:0] mpi_clk mpi_rw mpi_ack mpi_irq mpi_ale mpi_be1 hdc ldc to daisy- chained devices orca 8 fpga series 3 done init ad[7:0] clkin w/r rdyrcv xint x ale be1 i960 cs1 cs0 i960 system clock v dd mpi_be0 be0 mpi_strb ads power on with write configuration read status register init = 1? no read status register bit stream error? data_rdy = 1? write data to done = 1? done error yes yes yes no no yes no valid m[3:0] control register bits configuration data reg select devices have been discontinued. see ordering information section for product status.
94 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas fpga con?uration modes (continued) 5-5764(f) figure 60. readback through mpi enable microprocessor set readback address write rd_cfg to 0 data_rdy = 1? read data register start of frame data = 0xff? yes yes read status register in control register 1 interface in user mode read data register found? read until end of frame finished readback? yes yes write rd_cfg control stop no no error no error no read data register data = 0xff? yes no error to 1 in register 1 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 95 data sheet november 2006 orca series 3c and 3t fpgas fpga con?uration modes (continued) slave serial mode the slave serial mode is primarily used when multiple fpgas are con?ured in a daisy-chain (see the daisy- chaining section). it is also used on the fpga evalua- tion board that interfaces to the download cable. a device in the slave serial mode can be used as the lead device in a daisy-chain. figure 61 shows the connec- tions for the slave serial con?uration mode. the con?uration data is provided into the fpgas din input synchronous with the con?uration clock cclk input. after the fpga has loaded its con?uration data, it retransmits the incoming con?uration data on dout. cclk is routed into all slave serial mode devices in parallel. multiple slave fpgas can be loaded with identical con- ?urations simultaneously. this is done by loading the con?uration data into the din inputs in parallel. 5-4485(f) figure 61. slave serial con?uration schematic slave parallel mode the slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins d[7:0] for each cclk cycle. due to 8 bits of data being input per cclk cycle, the dout pin does not contain a valid bit stream for slave parallel mode. as a result, the lead device cannot be used in the slave parallel mode in a daisy-chain con?uration. figure 62 is a schematic of the connections for the slave parallel con?uration mode. wr and cs0 are active-low chip select signals, and cs1 is an active- high chip select signal. these chip selects allow the user to con?ure multiple fpgas in slave parallel mode using an 8-bit data bus common to all of the fpgas. these chip selects can then be used to select the fpga(s) to be con?ured with a given bit stream. the chip selects must be active for each valid cclk cycle until the device has been completely pro- grammed. they can be inactive between cycles but must meet the setup and hold times for each valid pos- itive cclk. d[7:0] of the fpga can be connected to d[7:0] of the microprocessor only if a standard prom ?e format is used. if a .bit or .rbt ?e is used from isplever, then the user must mirror the bytes in the .bit or .rbt ?e or leave the .bit or .rbt ?e unchanged and connect d[7:0] of the fpga to d[0:7] of the micro- processor. 5-4487(f) figure 62. slave parallel con?uration schematic micro- processor or download cable m2 m1 m0 hdc series fpga ldc v dd cclk prgm dout to daisy- chained devices done din init orca micro- processor or system d[7:0] done cclk cs1 m2 m1 m0 hdc ldc 8 v dd init prgm cs0 wr series fpga orca select devices have been discontinued. see ordering information section for product status.
96 96 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas fpga con?uration modes (continued) daisy-chaining multiple fpgas can be con?ured by using a daisy- chain of the fpgas. daisy-chaining uses a lead fpga and one or more fpgas con?ured in slave serial mode. the lead fpga can be con?ured in any mode except slave parallel mode. (daisy-chaining is available with the boundary-scan ram_w instruction discussed later.) all daisy-chained fpgas are connected in series. each fpga reads and shifts the preamble and length count in on positive cclk and out on negative cclk edges. an upstream fpga that has received the preamble and length count outputs a high on dout until it has received the appropriate number of data frames so that downstream fpgas do not receive frame start bit pairs. after loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its con?uration data frames. the loading of con?uration data continues after the lead device has received its con?uration data if its internal frame bit counter has not reached the length count. when the con?uration ram is full and the num- ber of bits received is less than the length count ?ld, the fpga shifts any additional data out on dout. the con?uration data is read into din of slave devices on the positive edge of cclk, and shifted out dout on the negative edge of cclk. figure 63 shows the connections for loading multiple fpgas in a daisy- chain con?uration. the generation of cclk for the daisy-chained devices that are in slave serial mode differs depending on the con?uration mode of the lead device. a master paral- lel mode device uses its internal timing generator to produce an internal cclk at eight times its memory address rate (rclk). the asynchronous peripheral mode device outputs eight cclks for each write cycle. if the lead device is con?ured in slave mode, cclk must be routed to the lead device and to all of the daisy-chained devices. 5-4488(f figure 63. daisy-chain con?uration schematic as seen in figure 63, the init pins for all of the fpgas are connected together. this is required to guarantee that powerup and initialization will work correctly. in general, the done pins for all of the fpgas are also connected together as shown to guarantee that all of the fpgas enter the start-up state simultaneously. this may not be required, depending upon the start-up sequence desired. v dd eprom program d[7:0] oe ce a[17:0] a[17:0] d[7:0] done m2 m1 m0 done hdc ldc rclk cclk dout din dout din cclk done dout init init init cclk v dd v dd or gnd prgm prgm m2 m1 m0 prgm m2 m1 m0 v dd v dd hdc ldc rclk hdc ldc rclk v dd orca series fpga slave #2 orca series fpga master orca series fpga slave #1 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 97 data sheet november 2006 orca series 3c and 3t fpgas fpga con?uration modes (continued) daisy-chaining with boundary scan multiple fpgas can be con?ured through the jtag ports by using a daisy-chain of the fpgas. this daisy-chain- ing operation is available upon initial con?uration after powerup, after a power-on reset, after pulling the program pin to reset the chip, or during a recon?uration if the en_jtag ram has been set. all daisy-chained fpgas are connected in series. each fpga reads and shifts the preamble and length count in on the positive tck and out on the negative tck edges. an upstream fpga that has received the preamble and length count outputs a high on tdo until it has received the appropriate number of data frames so that downstream fpgas do not receive frame start bit pairs. after load- ing and retransmitting the preamble and length count to a daisy-chain of downstream devices, the lead device loads its con?uration data frames. the loading of con?uration data continues after the lead device had received its con?uration read into tdi of downstream devices on the positive edge of tck, and shifted out tdo on the negative edge of tck. figure 63 shows the connections for loading multiple fpgas in a jtag daisy-chain con?uration. select devices have been discontinued. see ordering information section for product status.
98 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series fpgas include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. table 35. absolute maximum ratings recommended operating conditions table 36. recommended operating conditions note: the maximum recommended junction temperature (t j ) during operation is 125 ?. parameter symbol min max unit storage temperature t stg ?5 150 ? supply voltage with respect to ground v dd ?.5 7.0 v input signal with respect to ground ?.5 v dd + 0.3 v signal applied to high-impedance output ?.5 v dd + 0.3 v maximum package body temperature 220 ? mode or3cxx or3txxx temperature range (ambient) supply voltage (v dd ) temperature range (ambient) supply voltage (v dd ) commercial 0 ? to 70 ? 5 v ?5% 0 ? to 70 ? 3.0 v to 3.6 v industrial ?0 ? to +85 ? 5 v ?10% ?0 ? to +85 ? 3.0 v to 3.6 v select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 99 data sheet november 2006 orca series 3c and 3t fpgas electrical characteristics table 37. electrical characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ? . parameter sym- bol test conditions or3cxx or3txxx unit min max min max input voltage: high low v ih v il input con?ured as cmos (includes or3txxx) 50% v dd gnd ?0.5 v dd + 0.5 20% v dd 50% v dd gnd ?0.5 v dd + 0.5 30% v dd v v input voltage: high low v ih v il or3txxx 5 v tolerant 50% v dd gnd ?0.5 5.8 v 30% v dd v v input voltage: high low v ih v il input con?ured as ttl (not valid for or3txxx) 2.0 0.5 v dd + 0.3 0.8 ? v v output voltage: high low v oh v ol v dd = min, i oh = 6 ma or 3 ma v dd = min, i ol = 12 ma or 6 ma 2.4 0.4 2.4 0.4 v v input leakage current i l v dd = max, v in = v ss or v dd ?0 10 ?0 10 ? standby current: or3t20 or3t30 or3t55 or3c/t80 or3t125 i ddsb or3cxx (t a = 25 ?, v dd = 5.0 v) or3txxx (t a = 25 ?, v dd = 3.3 v) internal oscillator running, no out- put loads, inputs v dd or gnd (after conguration) 4.06 4.56 4.70 4.90 5.30 5.80 6.70 ma ma ma ma ma standby current: or3t20 or3t30 or3t55 or3c/t80 or3t125 i ddsb or3cxx (t a = 25 ?, v dd = 5.0 v) or3txxx (t a = 25 ?, v dd = 3.3 v) internal oscillator stopped, no output loads, inputs v dd or gnd (after conguration) 3.05 3.42 3.52 3.68 3.98 4.35 5.02 ma ma ma ma ma powerup current: or3t20 or3t30 or3t55 or3c/t80 or3t125 ipp power supply current @ approxi- mately 1 v, within a recommended power supply ramp rate of 1 ms?00 ms 3.2 5.4 1.2 1.6 2.7 4.0 6.5 ma ma ma ma ma data retention voltage v dr t a = 25 ? 2.3 2.3 v input capacitance c in or3cxx (t a = 25 ?, v dd = 5.0 v) or3txxx (t a = 25 ?, v dd = 3.3 v) test frequency = 1 mhz ? 8pf output capacitance c out or3cxx (t a = 25 ?, v dd = 5.0 v) or3txxx (t a = 25 ?, v dd = 3.3 v) test frequency = 1 mhz ? 8pf select devices have been discontinued. see ordering information section for product status.
100 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas electrical characteristics (continued) table 37. electrical characteristics (continued) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. * on the or3txxx devices, the pull-up resistor will externally pull the pin to a level 1.0 v below v dd . note: for 3t devices driven to 5 v. parameter symbol test conditions or3cxx or3txxx unit min max min max done pull-up resistor* r done 100 100 k m[3:0] pull-up resistors* r m 100 100 k i/o pad static pull-up current* i pu or3cxx (v dd = 5.25 v, v in = v ss , t a = 0 ?) or3txxx (v dd = 3.6 v, v in = v ss , t a = 0 ?) 14.4 50.9 14.4 50.9 ? i/o pad static pull-down current i pd or3cxx (v dd = 5.25 v, v in = v ss , t a = 0 ?) or3txxx (v dd = 3.6 v, v in = v ss , t a = 0 ?) 26 103 26 103 ? i/o pad pull-up resistor* r pu v dd = all, v in = v ss , t a = 0 ? 100 100 k i/o pad pull-down resistor r pd v dd = all, v in = v dd , t a = 0 ? 50 50 k select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 101 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics description to de?e speed grades, the orca series part number designation (see ordering information) uses a single- digit number to designate a speed grade. this number is not related to any single ac parameter. higher num- bers indicate a faster set of timing parameters. the actual speed sorting is based on testing the delay in a path consisting of an input buffer, combinatorial delay through all plcs in a row, and an output buffer. other tests are then done to verify other delay parameters, such as routing delays, setup times to ffs, etc. the most accurate timing characteristics are reported by the timing analyzer in the isplever development system. a timing report provided by the development system after layout divides path delays into logic and routing delays. the timing analyzer can also provide logic delays prior to layout. while this allows routing budget estimates, there is wide variance in routing delays associated with different layouts. the logic timing parameters noted in the electrical characteristics section of this data sheet are the same as those in the design tools. in the pfu timing given in table 41?able 48, symbol names are generally a concatenation of the pfu operating mode (as de?ed in table 3) and the parameter type. the setup, hold, and propagation delay parameters, de?ed below, are designated in the symbol name by the set, hld, and del characters, respectively. the values given for the parameters are the same as those used during production testing and speed bin- ning of the devices. the junction temperature and sup- ply voltage used to characterize the devices are listed in the delay tables. actual delays at nominal tempera- ture and voltage for best-case processes can be much better than the values given. it should be noted that the junction temperature used in the tables is generally 85 ?. the junction temperature for the fpga depends on the power dissipated by the device, the package thermal characteristics ( ja ), and the ambient temperature, as calculated in the following equation and as discussed further in the package thermal characteristics section: t jmax = t amax + (p ? ja ) ? note : the user must determine this junction tempera- ture to see if the delays from isplever should be derated based on the following derating tables. table 38 and table 39 provide approximate power sup- ply and junction temperature derating for or3cxx com- mercial and industrial devices. table 40 provides the same information for the or3txxx devices (both com- mercial and industrial). the delay values in this data sheet and reported by isplever are shown as 1.00 in the tables. the method for determining the maximum junction temperature is de?ed in the package thermal characteristics section. taken cumulatively, the range of parameter values for best-case vs. worst-case pro- cessing, supply voltage, and junction temperature can approach 3 to 1. table 38 . derating for commercial devices (or3cxx) table 39 . derating for industrial devices (or3cxx) table 40. derating for commercial/industrial devices (or3txxx) note: the derating tables shown above are for a typical critical path that contains 33% logic delay and 66% routing delay. since the routing delay derates at a higher rate than the logic delay, paths with more than 66% routing delay will derate at a higher rate than shown in the table. the approximate derating values vs. temperature are 0.26% per ? for logic delay and 0.45% per ? for routing delay. the approximate derating values vs. voltage are 0.13% per mv for both logic and routing delays at 25 ?. t j (?) power supply voltage 4.75 v 5.0 v 5.25 v 0 0.81 0.79 0.77 25 0.85 0.83 0.81 85 1.00 0.97 0.95 100 1.05 1.02 1.00 125 1.12 1.09 1.07 t j (?) power supply voltage 4.5 v 4.75 v 5.0 v 5.25 v 5.5 v ?40 0.71 0.70 0.68 0.66 0.65 0 0.80 0.78 0.76 0.74 0.73 25 0.84 0.82 0.80 0.78 0.77 85 1.00 0.97 0.94 0.93 0.91 100 1.05 1.01 0.99 0.97 0.95 125 1.12 1.09 1.06 1.04 1.02 t j (?) power supply voltage 3.0 v 3.3 v 3.6 v ?40 0.73 0.66 0.61 0 0.82 0.73 0.68 25 0.87 0.78 0.72 85 1.00 0.90 0.83 100 1.04 0.94 0.87 125 1.10 1.00 0.92 select devices have been discontinued. see ordering information section for product status.
102 102 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) in addition to supply voltage, process variation, and operating temperature, circuit and process improve- ments of the orca series fpgas over time will result in signi?ant improvement of the actual performance over those listed for a speed grade. even though lower speed grades may still be available, the distribution of yield to timing parameters may be several speed grades higher than that designated on a product brand. design practices need to consider best-case timing parameters (e.g., delays = 0), as well as worst-case timing. the routing delays are a function of fan-out and the capacitance associated with the cips and metal inter- connect in the path. the number of logic elements that can be driven (fan-out) by pfus is unlimited, although the delay to reach a valid logic level can exceed timing requirements. it is dif?ult to make accurate routing delay estimates prior to design compilation based on fan-out. this is because the cae software may delete redundant logic inserted by the designer to reduce fan- out, and/or it may also automatically reduce fan-out by net splitting. the waveform test points are given in the input/output buffer measurement conditions section of this data sheet. the timing parameters given in the electrical characteristics tables in this data sheet follow industry practices, and the values they re?ct are described below. propagation delay ?he time between the speci?d reference points. the delays provided are the worst case of the tphh and tpll delays for noninverting func- tions, tplh and tphl for inverting functions, and tphz and tplz for 3-state enable. setup time ?he interval immediately preceding the transition of a clock or latch enable signal, during which the data must be stable to ensure it is recognized as the intended value. hold time ?he interval immediately following the transition of a clock or latch enable signal, during which the data must be held stable to ensure it is recognized as the intended value. 3-state enable ?he time from when a 3-state control signal becomes active and the output pad reaches the high-impedance state. pfu timing * four-input variables (k z [3:0]) path delays are valid for luts in both f4 (four-input lut) and f5 (?e-input lut) modes. table 41. combinatorial pfu timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max combinatorial delays (t j = +85 ?, v dd = min): four-input variables (kz[3:0] to f[z])* five-input variables (f5[a:d] to f[0, 2, 4, 6]) two-level lut delay (kz[3:0] to f w/feedbk)* two-level lut delay (f5[a:d] to f w/feedbk) three-level lut delay (kz[3:0] to f w/feedbk)* three-level lut delay (f5[a:d] to f w/feedbk) c in to c out delay (logic mode) f4_del f5_del swl2_del swl2f5_del swl3_del swl3f5_del co_del 2.34 2.11 4.87 4.69 6.93 6.89 3.47 1.80 1.57 3.66 3.51 5.15 5.08 2.65 1.32 1.23 2.58 2.48 3.63 3.54 1.79 1.05 0.99 2.03 1.94 2.82 2.75 1.43 ns ns ns ns ns ns ns select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 103 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) note: see table 46 for an explanation of fdbk_del and omux_del. 5-5751(f) figure 64. combinatorial pfu timing f4_del lut f4_del/ f5_del lut f5?el lut f4_del/ lut f4_del/ f5_del lut f4_del/ f5_del lut f4_del/ lut f4_del/ f5_del lut f4_del/ f5_del lut f4_del/ f5_del lut f4_del/ f5_del lut f4_del/ f5_del lut k z [3:0] k z [3:0], f5[a:d] k z [3:0] k z [3:0] f5[a:d] f5[a:d] f[7:0] f[6, 4, f[7:0] f[7:0] f[7:0] f[7:0] fdbk?el o[9:0] swl2_del swl3_del swl2f5_del swl3f5_del pfu 8 4 omux_del 2, 0] select devices have been discontinued. see ordering information section for product status.
104 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 42. sequential pfu timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ? . parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max input requirements clock low time clkl_mpw 3.36 2.07 0.94 0.72 ns clock high time clkh_mpw 1.61 1.06 0.54 0.45 ns global s/r pulse width (gsrn) gsr_mpw 3.36 2.07 0.94 0.72 ns local s/r pulse width lsr_mpw 3.36 2.07 0.94 0.72 ns combinatorial setup times (t j = +85 ?, v dd = min): four-input variables to clock (kz[3:0] to clk)* five-input variables to clock (f5[a:d] to clk) data in to clock (din[7:0] to clk) carry-in to clock, direct to regcout (cin to clk) clock enable to clock (ce to clk) clock enable to clock (aswe to clk) local set/reset to clock (sync) (lsr to clk) data select to clock (sel to clk) two-level lut to clock (kz[3:0] to clk w/feedbk)* two-level lut to clock (f5[a:d] to clk w/feedbk) three-level lut to clock (kz[3:0] to clk w/feedbk)* three-level lut to clock (f5[a:d] to clk w/feedbk) f4_set f5_set din_set cindir_set ce1_set ce2_set lsr_set sel_set swl2_set swl2f5_set swl3_set swl3f5_set 1.99 1.79 0.47 1.25 2.86 1.68 1.86 1.37 3.98 4.06 6.49 6.39 1.47 1.33 0.32 0.99 2.15 1.30 1.36 1.00 2.99 2.97 4.81 4.73 1.08 1.03 0.18 0.71 1.80 0.95 0.86 0.92 2.13 2.29 3.42 3.34 0.85 0.81 0.16 0.58 1.37 0.77 0.68 0.70 1.63 1.68 2.64 2.57 ns ns ns ns ns ns ns ns ns ns ns ns combinatorial hold times (t j = all, v dd = all): data in (din[7:0] from clk) carry-in from clock, direct to regcout (cin from clk) clock enable (ce from clk) clock enable from clock (aswe from clk) local set/reset from clock (sync) (lsr from clk) data select from clock (sel from clk) all others din_hld cindir_hld ce1_hld ce2_hld lsr_hld sel_hld 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns ns ns output characteristics sequential delays (t j = +85 ?, v dd = min): local s/r (async) to pfu out (lsr to q[7:0], reg- cout) global s/r to pfu out (gsrn to q[7:0], regcout) clock to pfu out?egister (clk to q[7:0], reg- cout) clock to pfu out?atch (clk to q[7:0]) transparent latch (din[7:0] to q[7:0]) lsr_del gsr_del reg_del ltch_del ltchd_del 7.02 5.21 2.38 2.51 2.73 5.29 3.90 1.75 1.88 2.10 3.64 2.55 1.26 1.21 1.38 2.90 2.00 0.97 0.96 1.12 ns ns ns ns ns * four-input variables (k z [3:0]) setup times are valid for luts in both f4 (four-input lut) and f5 (?e-input lut) modes. note: the table shows worst-case delays. isplever reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 105 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 43. ripple mode pfu timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ? . parameter (t j = +85 ?, v dd = min) symbol speed unit -4 -5 -6 -7 min max min max min max min max full ripple setup times (byte wide): operands to clock (kz[1:0] to clk) bitwise operands to clock (kz[1:0] to clk at f[z]) fast carry-in to clock (fcin to clk) carry-in to clock (cin to clk) add/subtract to clock (aswe to clk) operands to clock (kz[1:0] to clk at regcout) fast carry-in to clock (fcin to clk at regcout) carry-in to clock (cin to clk at regcout) add/subtract to clock (aswe to clk at regcout) rip_set frip_set fcin_set cin_set as_set riprc_set fcinrc_set cinrc_set asrc_set 3.50 1.99 2.55 3.80 8.82 2.09 2.29 3.09 8.14 2.50 1.47 1.87 2.79 6.18 1.61 1.76 2.36 5.73 1.96 1.08 1.34 1.97 4.68 1.19 1.28 1.73 4.54 1.48 0.85 1.04 1.56 3.50 0.93 1.02 1.35 3.39 ns ns ns ns ns ns ns ns ns full ripple hold times (t j = all, v dd = all): fast carry-in from clock (fcin from clk at reg- cout) all others fcinrc_hld generic_hld 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns half ripple setup times (nibble wide): operands to clock (kz[1:0] to clk) bitwise operands to clock (kz[1:0] to clk at f[z]) fast carry-in to clock (fcin to clk) carry-in to clock (cin to clk) add/subtract to clock (aswe to clk) operands to clock (kz[1:0] to clk at regcout) fast carry-in to clock (fcin to clk at regcout) carry-in to clock (cin to clk at regcout) add/subtract to clock (aswe to clk at regcout) hrip_set hfrip_set hfcin_set hcin_set has_set hriprc_set hfcinrc_set hcinrc_set hasrc_set 3.91 1.99 2.55 3.80 8.82 3.03 2.29 3.09 8.14 2.81 1.47 1.87 2.79 6.18 2.31 1.76 2.36 5.73 2.21 1.08 1.34 1.97 4.68 1.68 1.28 1.73 4.54 1.66 0.85 1.04 1.56 3.50 1.32 1.02 1.35 3.39 ns ns ns ns ns ns ns ns ns half ripple hold times (t j = all, v dd = all): fast carry-in from clock (hfcin from clk at reg- cout) all others hfcinrc_hld generic_hld 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns note: the table shows worst-case delay for the ripple chain. isplever reports the delay for individual paths within the ripple chain that will be less than or equal to those listed above. select devices have been discontinued. see ordering information section for product status.
106 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 43. ripple mode pfu timing characteristics (continued) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ? . parameter (t j = +85 ?, v dd = min) symbol speed unit -4 -5 -6 -7 min max min max min max min max full ripple delays (byte wide): operands to carry-out (kz[1:0] to cout) operands to carry-out (kz[1:0] to fcout) operands to pfu out (kz[1:0] to f[7:0]) bitwise operands to pfu out (kz[1:0] to f[z]) fast carry-in to carry-out (fcin to cout) fast carry-in to fast carry-out (fcin to fcout) carry-in to carry-out (cin to cout) carry-in to fast carry-out (cin to fcout) fast carry-in pfu out (fcin to f[7:0]) carry-in pfu out (cin to f[7:0]) add/subtract to carry-out (aswe to cout) add/subtract to carry-out (aswe to fcout) add/subtract to pfu out (aswe to f[7:0]) ripco_del ripfco_del rip_del frip_del fcinco_del fcinfco_del cinco_del cinfco_del fcin_del cin_del asco_del asfco_del as_del 5.32 5.30 7.37 2.34 2.59 2.57 3.47 3.46 6.03 6.91 8.28 8.11 10.66 4.11 4.10 5.60 1.80 1.99 1.98 2.65 2.64 4.55 5.21 5.89 5.78 7.55 2.98 2.98 4.18 1.32 1.43 1.41 1.79 1.78 3.21 3.53 4.58 4.48 5.85 2.32 2.32 3.10 1.05 1.14 1.13 1.43 1.43 2.51 3.05 3.45 3.38 4.38 ns ns ns ns ns ns ns ns ns ns ns ns ns half ripple delays (nibble wide): operands to carry-out (kz[1:0] to cout) operands to fast carry-out (kz[1:0] to fcout) operands to pfu out (kz[1:0] to f[3:0]) bitwise operands to pfu out (kz[1:0] to f[z]) fast carry-in to carry-out (fcin to cout) fast carry-in to fast carry-out (fcin to fcout) carry-in to carry-out (cin to cout) carry-in to carry-out (cin to fcout) fast carry-in pfu out (fcin to f[3:0]) carry-in pfu out (cin to f[3:0]) add/subtract to carry-out (aswe to cout) add/subtract to carry-out (aswe to fcout) add/subtract to pfu out (aswe to f[3:0]) hripco_del hripfco_del hrip_del hfrip_del hfcinco_del hfcinfco_del hcinco_del hcinfco_del hfcin_del hcin_del hasco_del hasfco_del has_del 5.32 5.30 5.50 2.34 2.59 2.57 3.47 3.46 3.76 4.65 8.28 8.11 9.12 4.11 4.10 4.07 1.80 1.99 1.98 2.65 2.64 2.84 3.50 5.89 5.78 6.49 2.98 2.98 3.20 1.32 1.43 1.41 1.79 1.78 2.01 2.33 4.58 4.48 4.86 2.32 2.32 2.40 1.05 1.14 1.13 1.43 1.43 1.58 2.12 3.45 3.38 3.69 ns ns ns ns ns ns ns ns ns ns ns ns ns note: the table shows worst-case delay for the ripple chain. isplever reports the delay for individual paths within the ripple chain that will be less than or equal to those listed above. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 107 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 44. synchronous memory write characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. * the ram is written on the inactive clock edge following the active edge that latches the address, data, and control signals. note: the table shows worst-case delays. isplever reports the delays for individual paths within a group of paths representing the same tim- ing parameter and may accurately report delays that are less than those listed. 5-4621(f) figure 65. synchronous memory write characteristics parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max write operation for ram mode: maximum frequency clock low time clock high time clock to data valid (clk to f[6, 4, 2, 0])* smclk_frq smclkl_mpw smclkh_mpw mem_del 2.34 3.79 151.00 10.00 1.80 2.77 197.00 7.14 1.32 2.13 254.00 5.00 1.05 1.62 315.00 4.08 mhz ns ns ns write operation setup time: address to clock (cin to clk) address to clock (din[7, 5, 3, 1] to clk) data to clock (din[6, 4, 2, 0] to clk) write enable (wren) to clock (aswe to clk) write-port enable 0 (wpe0) to clock (ce to clk) write-port enable 1 (wpe1) to clock (lsr to clk) wa4_set wa_set wd_set we_set wpe0_set wpe1_set 1.25 0.72 0.02 0.18 2.25 2.79 0.99 0.52 0.06 0.16 1.69 2.13 0.71 0.35 0.00 0.14 1.16 1.58 0.58 0.28 0.00 0.12 0.84 1.31 ns ns ns ns ns ns write operation hold time: address from clock (cin from clk) address from clock (din[7, 5, 3, 1] from clk) data from clock (din[6, 4, 2, 0] from clk) write enable (wren) from clock (aswe from clk) write-port enable 0 (wpe0) from clock (ce from clk) write-port enable 1 (wpe1) from clock (lsr from clk) wa4_hld wa_hld wd_hld we_hld wpe0_hld wpe1_hld 0.00 0.00 0.59 0.03 0.00 0.00 0.00 0.00 0.42 0.00 0.00 0.00 0.00 0.00 0.40 0.08 0.00 0.00 0.00 0.00 0.32 0.06 0.00 0.00 ns ns ns ns ns ns ck f[6, 4, 2, 0] cin, din[7, 5, 3, 1] din[6, 4, 2, 0] mem_del wa4_set aswe (wren) ce (wpe0), t sch t scl wa4_hld wd_set wd_hld we_set we_hld wpe0_set wpe0_hld wa_set wa_hld wpe1_set wpe1_hld lsr (wpe1) select devices have been discontinued. see ordering information section for product status.
108 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 45. synchronous memory read characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. note: the table shows worst-case delays. isplever reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. 5-4622(f) figure 66. synchronous memory read cycle parameter (t j = 85 ?, v dd = min) symbol speed unit -4 -5 -6 -7 min max min max min max min max read operation: data valid after address (kz[3:0] to f[6, 4, 2, 0]) data valid after address (f5[a:d] to f[6, 4, 2, 0]) ra_del ra4_del 2.34 2.11 1.80 1.57 1.32 1.23 1.05 0.99 ns ns read operation, clocking data into latch/ff: address to clock setup time (kz[3:0] to clk) address to clock setup time (f5[a:d] to clk) address from clock hold time (kz[3:0] from clk) address from clock hold time (f5[a:d] from clk) clock to pfu output?egister (clk to q[6, 4, 2, 0]) read cycle delay ra_set ra4_set ra_hld ra4_hld reg_del smrd_cyc 1.99 1.79 0.00 0.00 2.38 10.48 1.47 1.33 0.00 0.00 1.75 7.66 1.08 1.03 0.00 0.00 1.26 7.53 0.85 0.81 0.00 0.00 0.97 5.78 ns ns ns ns ns ns kz[3:0], f5[a:d] f[6, 4, 2, 0] clk q[3:0] ra_del ra4_del ra_set ra4_set reg_del ra_hld ra4_hld smrd_cyc select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 109 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) plc timing table 46. pfu output mux and direct routing timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. * this is general feedback using switching segments. see the combinatorial pfu timing table for softwired look-up table feedback timing. slic timing table 47 . supplemental logic and interconnect cell (slic) timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. parameter (t j = 85 ?, v dd = min) symbol speed unit -4 -5 -6 -7 min max min max min max min max pfu output mux (fan-out = 1) output mux delay (f[7:0]/q[7:0] to o[9:0]) carry-out mux delay (cout to o9) registered carry-out mux delay (regcout to o8) omux_del coo9_del rcoo8_del 0.50 0.34 0.34 0.39 0.26 0.26 0.35 0.24 0.24 0.28 0.18 0.18 ns ns ns direct routing pfu feedback (xsw)* pfu to orthogonal pfu delay (xsw to xsw) pfu to diagonal pfu delay (xbid to xsw) fdbk_del odir_del ddir_del 1.74 2.21 2.69 1.41 1.77 2.19 1.48 1.75 2.53 1.14 1.39 1.98 ns ns ns parameter (t j = 85 ?, v dd = min) symbol speed unit -4 -5 -6 -7 min max min max min max min max 3-statable bidis bidi delay (brx to blx, blx to brx) bidi delay (ox to brx, ox to blx) bidi 3-state enable/disable delay (tri to bl, br) bidi 3-state enable/disable delay (bl, br via dec, tri to bl, br) buf_del obuf_del tri_del dectri_del 0.84 0.72 2.55 3.59 0.70 0.61 1.90 2.65 0.94 0.87 1.31 1.91 0.77 0.70 1.01 1.48 ns ns ns ns decoder decoder delay (br[9:8], bl[9:8] to dec) decoder delay (br[7:0], bl[7:0] to dec) dec98_del dec_del 2.39 2.35 1.85 1.82 1.27 1.23 1.02 0.99 ns ns select devices have been discontinued. see ordering information section for product status.
110 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) pio timing table 48. programmable i/o (pio) timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max input delays (t j = 85 ?, v dd = min) input rise time in_ris 500 500 500 500 ns input fall time in_fal 500 500 500 500 ns pio direct delays: pad to in (pad to clk in) pad to in (pad to in1, in2) pad to in delayed (pad to in1, in2) ckin_del in_del ind_del 1.41 2.16 9.05 1.26 1.87 7.83 0.64 1.28 6.64 0.41 0.90 7.27 ns ns ns pio transparent latch delays: pad to in (pad to in1, in2) pad to in delayed (pad to in1, in2) latch_del latchd_del 4.11 10.58 3.25 9.05 2.52 7.67 1.82 7.65 ns ns input latch/ff setup timing: pad to expressclk (fast-capture latch/ff) pad delayed to expressclk (fast-capture latch/ff) pad to clock (input latch/ff) pad delayed to clock (input latch/ff) clock enable to clock (ce to clk) local set/reset (sync) to clock (lsr to clk) inrege_set inreged_set inreg_set inregd_set ince_set inlsr_set 5.93 12.86 1.62 8.57 2.03 1.79 4.82 11.03 1.42 7.36 1.64 1.45 3.63 9.18 0.71 5.91 1.29 1.14 3.23 9.68 0.50 7.06 1.00 0.89 ns ns ns ns ns ns input ff/latch hold timing: pad from expressclk (fast-capture latch/ff) pad delayed from expressclk (fast-capture latch/ff) pad from clock (input latch/ff) pad delayed from clock (input latch/ff) clock enable from clock (ce from clk) local set/reset (sync) from clock (lsr from clk) inrege_hld inreged_hld inreg_hld inregd_hld ince_hld inlsr_hld 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns ns clock-to-in delay (ff clk to in1, in2) clock-to-in delay (latch clk to in1, in2) local s/r (async) to in (lsr to in1, in2) local s/r (async) to in (lsr to in1, in2) latchff in latch mode global s/r to in (gsrn to in1, in2) inreg_del inltch_del inlsr_del inlsrl_del ingsr_del 4.05 4.08 6.11 5.89 5.38 3.14 3.19 4.76 4.66 4.22 2.53 2.62 3.81 3.57 3.44 2.05 2.14 3.17 2.98 2.88 ns ns ns ns ns note: the delays for all input buffers assume an input rise/fall time of < 1 v/ns. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 111 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 48. programmable i/o (pio) timing characteristics (continued) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max output delays (t j = 85 ?, v dd = min, c l = 50 pf) output to pad (out2, out1 direct to pad): fast slewlim sinklim outf_del outsl_del outsi_del 5.09 7.86 9.41 4.21 6.49 7.98 2.63 3.49 8.08 2.17 2.91 7.32 ns ns ns 3-state enable/disable delay (ts to pad): fast slewlim sinklim tsf_del tssl_del tssi_del 4.93 7.70 9.25 4.09 6.37 7.86 2.33 3.00 7.95 1.88 2.41 7.23 ns ns ns local set/reset (async) to pad (lsr to pad): fast slewlim sinklim outlsrf_del outlsrsl_del outlsrsi_del 9.03 11.79 13.35 7.25 9.53 11.02 4.96 5.82 10.38 3.94 4.67 9.10 ns ns ns global set/reset to pad (gsrn to pad): fast slewlim sinklim outgsrf_del outgsrsl_del outgsrsi_del 8.30 11.06 12.62 6.69 8.97 10.46 4.39 5.07 10.02 3.46 3.99 8.81 ns ns ns output ff setup timing: out to expressclk (out[2:1] to eclk) out to clock (out[2:1] to clk) clock enable to clock (ce to clk) local set/reset (sync) to clock (lsr to clk) oute_set out_set outce_set outlsr_set 0.00 0.00 0.91 0.41 0.00 0.00 0.67 0.32 0.00 0.00 0.56 0.26 0.00 0.00 0.45 0.24 ns ns ns ns output ff hold timing: out from expressclk (out[2:1] from eclk) out from clock (out[2:1] from clk) clock enable from clock (ce from clk) local set/reset (sync) from clock (lsr from clk) oute_hld out_hld outce_hld outlsr_hld 0.73 0.73 0.00 0.00 0.58 0.58 0.00 0.00 0.36 0.36 0.00 0.00 0.29 0.29 0.00 0.00 ns ns ns ns clock to pad delay (eclk, sclk to pad): fast slewlim sinklim outregf_del outregsl_del outregsi_del 6.71 9.47 11.03 5.44 7.71 9.20 3.56 4.42 8.98 2.78 3.52 7.94 ns ns ns additional delay if using open drain od_del 0.20 0.16 0.10 0.08 ns note: the delays for all input buffers assume an input rise/fall time of < 1 v/ns. select devices have been discontinued. see ordering information section for product status.
112 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 48. programmable i/o (pio) timing characteristics (continued) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max pio logic block delays out to pad (out[2:1] via logic to pad): fast slewlim sinklim outlf_del outlsl_del outlsi_del 5.09 7.86 9.41 4.21 6.49 7.98 2.63 3.49 8.08 2.17 2.91 7.32 ns ns ns outreg to pad (outreg via logic to pad): fast slewlim sinklim outrf_del outrsl_del outrsi_del 6.71 9.47 11.03 5.44 7.71 9.20 3.56 4.42 8.98 2.78 3.52 7.94 ns ns ns clock to pad (eclk, clk via logic to pad): fast slewlim sinklim outcf_del outcsl_del outcsi_del 6.97 9.74 11.29 5.68 7.96 9.45 3.71 4.57 9.13 2.91 3.64 8.07 ns ns ns 3-state ff delays 3-state enable/disable delay (ts direct to pad): fast slewlim sinklim tsf_del tssl_del tssi_del 4.93 7.70 9.25 4.09 6.37 7.86 2.33 3.00 7.95 1.88 2.41 7.23 ns ns ns local set/reset (async) to pad (lsr to pad): fast slewlim sinklim tslsrf_del tslsrsl_del tslsrsi_del 8.25 11.01 12.57 6.65 8.92 10.41 4.24 4.92 9.87 3.39 3.92 8.74 ns ns ns global set/reset to pad (gsrn to pad): fast slewlim sinklim tsgsrf_del tsgsrsl_del tsgsrsi_del 7.52 10.28 11.84 6.09 8.36 9.85 3.88 4.55 9.51 3.11 3.64 8.45 ns ns ns 3-state ff setup timing: ts to expressclk (ts to eclk) ts to clock (ts to clk) local set/reset (sync) to clock (lsr to clk) tse_set ts_set tslsr_set 0.00 0.00 0.28 0.00 0.00 0.21 0.00 0.00 0.17 0.00 0.00 0.18 ns ns ns 3-state ff hold timing: ts from expressclk (ts from eclk) ts from clock (ts from clk) local set/reset (sync) from clock (lsr from clk) tse_hld ts_hld tslsr_hld 0.85 0.85 0.00 0.68 0.68 0.00 0.44 0.44 0.00 0.34 0.34 0.00 ns ns ns clock to pad delay (eclk, sclk to pad): fast slewlim sinklim tsregf_del tsregsl_del tsregsi_del 5.94 8.70 10.26 4.82 7.10 8.59 2.84 3.52 8.47 2.23 2.76 7.58 ns ns ns note: the delays for all input buffers assume an input rise/fall time of < 1 v/ns. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 113 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) special function blocks timing table 49. microprocessor interface (mp i) timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. 1. for user system ?xibility, cs0 and cs1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when mpi_strb is low. if both chip selects are valid and the setup time is met, the mpi will latch the chip select state, and cs0 and cs1 may go inactive before the end of the read/write cycle. 2. 0.5 mpi_clk. 3. write data and w/r have to be valid starting from the clock cycle after both ads and cs0 and cs1 are recognized. 4. write data and w/r have to be held until the microprocessor receives a valid rd yrcv . notes: read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host ( powerpc , i960 ) from the fpga. powerpc and i960 timings to/from the clock are relative to the clock at the fpga microprocessor interface clock pin (mpi_clk). parameter symbol speed unit ? ? ? ? min max min max min max min max powerpc interface timing (t j = 85 ?, v dd = min) transfer acknowledge delay (clk to t a ) burst inhibit delay (clk to bin) transfer acknowledge delay to high impedance burst inhibit delay to high impedance write data setup time (data to ts ) write data hold time (data from clk while mpi_ack low) address setup time (addr to ts ) address hold time (addr from clk while mpi_a ck low) read/write setup time (r/w to ts ) read/write hold time (r/w from clk while mpi_a ck low) chip select setup time (cs0 , cs1 to ts ) chip select hold time (cs0 , cs1 from clk) user address delay (pad to ua[3:0]) user read/write delay (pad to urdwr_del) ta_del bi_del ta_delz bi_delz wd_set wd_hld a_set a_hld rw_set rw_hld cs_set cs_hld ua_del urdwr_del 0.0 0.0 0.0 0.0 0.0 0.0 0.3 0.0 11.6 11.6 (2) (2) 3.3 7.0 0.0 0.0 0.0 0.0 0.0 0.0 .25 0.0 9.3 9.3 (2) (2) 2.6 5.4 0.0 0.0 0.0 0.0 0.0 0.0 .14 0.0 8.0 8.0 (2) (2) 2.3 4.2 0.0 0.0 0.0 0.0 0.0 0.0 .12 0.0 6.8 6.8 (2) (2) 1.9 3.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns i960 interface timing (t j = 85 ?, v dd = min) addr/data select to ale (ads , to ale low) addr/data select to ale (ads , from ale low) ready/receive delay (clk to rd yrcv ) ready/receive delay to high impedance write data setup time write data hold time address setup time (addr to ale low) address hold time (addr from ale low) byte enable setup time (be0 , be1 to ale low) byte enable hold time (be0 , be1 from ale low) read/write setup time read/write hold time chip select setup time (cs0 , cs1 to clk) (1) chip select hold time (cs0 , cs1 from clk) (1) user address delay (clk low to ua[3:0]) user read/write delay (pad to urdwr_del) adsn_set adsn_hld rdyrcv_del rdyrcv_delz wd_set wd_hld a_set a_hld be_set be_hld rw_set rw_hld cs_set cs_hld ua_del urdwr_del 2.0 0.0 (3) (4) 2.0 2.0 2.0 2.0 (3) (4) 2.0 0.0 11.6 (2) 6.6 7.0 1.8 0.0 (3) (4) 1.8 1.8 1.8 1.8 (3) (4) 1.8 0.0 9.3 (2) 4.3 5.4 1.6 0.0 (3) (4) 0.50 0.51 0.50 0.51 (3) (4) 0.45 0.0 8.0 (2) 4.1 4.2 1.4 0.0 (3) (4) (3) (4) 0.0 6.8 (2) 0.42 0.44 0.42 0.44 0.38 3.5 3.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns select devices have been discontinued. see ordering information section for product status.
114 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 49. microprocessor interface (mp i) timing characteristics (continued) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. 1. for user system ?xibility, cs0 and cs1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when mpi_strb is low. if both chip selects are valid and the setup time is met, the mpi will latch the chip select state, and cs0 and cs1 may go inactive before the end of the read/write cycle. 2. 0.5 mpi_clk. 3. write data and w/r have to be valid starting from the clock cycle after both ads and cs0 and cs1 are recognized. 4. write data and w/r have to be held until the microprocessor receives a valid rd yrcv . 5. user logic delay has no prede?ed value. the user must generate a uend signal to complete the cycle. 6. ustart_del is based on the falling clock edge. 7. there is no speci? time associated with this delay. the user must assert uend low to complete this cycle. 8. the user must assert interrupt request low until a service routine is executed. 9. this should be at least one mpi_clk cycle. 10. user should set up read data so that rds_set and rds_hld can be met for the microprocessor timing. notes: read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host ( powerpc , i960 ) from the fpga. powerpc and i960 timings to/from the clock are relative to the clock at the fpga microprocessor interface clock pin (mpi_clk). parameter symbol speed unit ? ? ? ? min max min max min max min max user logic delay (5) user logic delay ns user start delay (mpi_clk falling to ustart) (6) ustart_del 3.6 3.4 3.3 2.8 ns user start clear delay (mpi_clk to ustart) ustartclr_del 7.5 7.3 7.1 6.0 ns user end delay (ustart low to uend low) (7) uend_del ns synchronous user timing: user end setup (uend to mpi_clk) uend_set 0.00 0.00 0.00 0.00 ns user end hold (uend to mpi_clk) uend_hld 1.0 0.95 0.88 0.75 ns data setup for read (d[7:0] to mpi_clk) (9) rds_set ns data hold for read (d[7:0] from mpi_clk) (9) rds_hld ns asynchronous user timing: user end to read data delay (uend to d[7:0]) (10) rda_del ns data hold from user start (low) (9) rda_hld ns interrupt request pulse width (8) tuirq_pw ns select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 115 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) 5-5832(f) figure 67. mpi powerpc user space read timing 5-5840(f) figure 68. mpi powerpc user space write timing mpi_clk a[4:0] mpi_rw (rd/wr ) cs0 , cs1 d[7:0] mpi_strb (ts ) ua[3:0] urdwrn ustart uend mpi_ack (ta ) mpi_bi (bi ) a_set rw_set cs_set urdwr_del rds_set a_hld cs_hld rds_hld rda_del rda_hld ustart_del user logic delay ta_del bi_del bi_del ta_del uend_del ustartclr_del rw_hld ua_del uend_set ta_delz bi_delz mpi_clk a[4:0] mpi_rw (rd/wr ) cs0 , cs1 d[7:0] mpi_strb (ts ) ua[3:0] urdwrn ustart uend mpi_ack (ta ) mpi_bi (bi ) a_set rw_set cs_set urdwr_del uend_set a_hld rw_hld cs_hld wd_hld ustart_del user logic delay ta_del bi_del bi_del ta_del uend_del ustartclr_del ua_del bi_delz ta_delz wd_set select devices have been discontinued. see ordering information section for product status.
116 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) 5-5832(f).c figure 69. mpi powerpc internal read timing 5-5840(f).e figure 70. mpi powerpc internal write timing mpi_clk a[4:0] mpi_rw (rd/wr ) cs0 , cs1 d[7:0] mpi_strb (ts ) ua[3:0] urdwrn mpi_ack (ta ) mpi_bi (bi ) a_set rw_set cs_set urdwr_del rds_set a_hld cs_hld rds_hld rda_del rda_hld ta_del bi_del bi_del ta_del rw_hld ua_del uend_set ta_delz bi_delz mpi_clk a[4:0] mpi_rw (rd/wr ) cs0 , cs1 d[7:0] mpi_strb (ts ) ua[3:0] urdwrn mpi_ack (ta ) mpi_bi (bi ) a_set rw_set cs_set urdwr_del a_hld rw_hld cs_hld wd_hld ta_del bi_del bi_del ta_del ua_del bi_delz ta_delz wd_set select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 117 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) 5-5831(f).b figure 71. mpi i960 user space read timing 5-5830(f).b figure 72. mpi i960 user space write timing mpi_clk d[7:0] mpi_rw (w/r ) cs0 , cs1 mpi_ale (ale) mpi_strb (ads ) ua[3:0] urdwrn ustart uend mpi_ack (rdyrcv ) adsn_hld a_set addr data ua_del uend_set rdyrcv_del ustart_del user logic delay rdyrcv_del uend_del ustartclr_del cs_hld rds_hld rw_hld rds_set rda_del rda_hld be0 , be1 be_hld be_set rdyrcv_delz urdwr_del adsn_set rw_set a_hld cs_set mpi_clk d[7:0] mpi_rw (w/r ) cs0 , cs1 mpi_ale (ale) mpi_strb (ads ) ua[3:0] urdwrn ustart uend mpi_ack (rdyrcv ) a_hld adsn_hld a_set data urdwr_del uend_set rdyrcv_del ustart_del user logic delay rdyrcv_del uend_del ustartclr_del cs_hld wd_hld rw_hld wd_set ua_del rdyrcv_delz addr cs_set rw_set adsn_set select devices have been discontinued. see ordering information section for product status.
118 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) 5-5831(f).c figure 73. mpi i960 internal read timing 5-5830(f).c figure 74. mpi i960 internal write timing mpi_clk d[7:0] mpi_rw (w/r ) cs0 , cs1 mpi_ale (ale) mpi_strb (ads ) ua[3:0] urdwrn mpi_ack (rdyrcv ) adsn_hld a_set addr data ua_del rdyrcv_del rdyrcv_del cs_hld rds_hld rw_hld rds_set rda_del rda_hld be0 , be1 be_hld be_set rdyrcv_delz urdwr_del adsn_set rw_set a_hld cs_set mpi_clk d[7:0] mpi_rw (w/r ) cs0 , cs1 mpi_ale (ale) mpi_strb (ads ) ua[3:0] urdwrn mpi_ack (rdyrcv ) a_hld adsn_hld a_set data urdwr_del rdyrcv_del rdyrcv_del cs_hld wd_hld rw_hld wd_set ua_del rdyrcv_delz addr cs_set rw_set adsn_set select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 119 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 50. programmable clock manager ( pcm ) timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. * input frequency tolerance is the allowed input clock frequency change in parts per million. ? see table 29 and table 30 for acquisition times for individual frequencies. pll mode, divider reg = 1111111 (input freq. = output freq.). parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max input clock frequency: fpcmi or3cxx 5 133 5 133 mhz or3txxx 5 133 5 133 5 133 mhz output clock frequency: fpcmo or3cxx 5 135 5 135 mhz or3txxx 5 100 5 100 5 100 mhz input clock duty cycle pcmi_duty 30.00 70.00 30.00 70.00 30.00 70.00 30.00 70.00 % output clock duty cycle pcmo_duty 3.13 96.90 3.13 96.90 3.13 96.90 3.13 96.90 % input frequency tolerance* ftol 26400 26400 26400 26400 ppm pcm acquisition time (clk in to lock) pcm_acq ? 36 100 36 100 36 100 36 100 ? pcm off delay (con?. done-l, we to pcm power off) pcmoff_del 100.0 100.0 100.0 100.0 ns pcm delay in dll mode (propagation delay) pcmdll-del 1.95 1.82 1.63 1.50 ns pcm delay in pll mode (propagation delay) pcmpll_del 0.00 0.00 0.00 0.00 ns pcm clock in to pcm clock out (clk in to eclk) pcmbye_del 0.47 0.36 0.26 0.24 ns pcm clock in to pcm clock out (clk in to sclk) pcmbys_del 0.47 0.36 0.26 0.24 ns routed clock-in delay (routing to pcm phase detect, using div0) rtckd_del 1.30 1.10 0.90 tbd ns system clock-out delay (pcm oscilla- tor to sclk output at pcm) pcmsck_del 2.70 2.20 1.90 tbd ns parameter symbol f out (mhz) pll mode dll mode unit output jitter outjit 5?0 250 200 ps 21?0 210 170 ps 31?0 180 145 ps 41?0 155 123 ps 51?0 130 105 ps 61?0 110 90 ps 71?0 95 75 ps 81?0 80 65 ps 91?00 70 55 ps select devices have been discontinued. see ordering information section for product status.
120 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 51. boundary-scan timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. 5-6764(f) figure 75. boundary-scan timing diagram parameter symbol min max unit tdi/tms to tck setup time t s 25.0 ns tdi/tms hold time from tck t h 0.0 ns tck low time t cl 50.0 ns tck high time t ch 50.0 ns tck to tdo delay t d 20.0 ns tck frequency t tck 10.0 mhz tck tms tdi tdo t s t h t d select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 121 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) clock timing table 52 . expressclk (eclk) and fast clock (fclk) timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. notes: the eclk delays are to all of the pics on one side of the device for middle pin input, or two sides of the device for corner pin input. the delay includes both the input buffer delay and the clock routing to the pic clock input. the fclk delays are for a fully routed clock tree that uses the expressclk input into the fast clock network. it includes both the input buffer delay and the clock routing to the pfu clk input. the delay will be reduced if any of the clock branches are not used. device (t j = 85 ?, v dd = min) symbol speed unit -4 -5 -6 -7 min max min max min max min max clock control timing delay through clkcntrl (input from corner) eclkc_del 0.31 0.31 0.31 0.31 ns delay through clkcntrl (input from inter- nal clock controller pad) eclkm_del 1.54 1.17 1.00 0.92 ns clock shutoff timing: setup from middle eclk (shut off to clk) hold from middle eclk (shut off from clk) setup from corner eclk (shut off to clk) hold from corner eclk (shut off from clk) offm_set offm_hld offc_set offc_hld 0.77 0.00 0.77 0.00 0.51 0.00 0.51 0.00 0.44 0.00 0.44 0.00 0.41 0.00 0.41 0.00 ns ns ns ns eclk delay (middle pad): or3t20 or3t30 or3t55 or3c/t80 or3t125 eclkm_del 3.50 3.67 2.56 2.62 2.74 2.86 3.06 2.05 2.08 2.13 2.19 2.29 1.78 1.80 1.85 1.90 1.98 ns ns ns ns ns eclk delay (corner pad): or3t20 or3t30 or3t55 or3c/t80 or3t125 eclkc_del 5.47 5.64 4.48 4.53 4.64 4.77 4.96 3.85 3.97 4.22 4.47 4.85 3.36 3.47 3.69 3.92 4.27 ns ns ns ns ns fclk delay (middle pad): or3t20 or3t30 or3t55 or3c/t80 or3t125 fclkm_del 8.24 8.87 5.91 6.12 6.59 7.11 7.98 4.59 4.66 4.83 5.01 5.33 3.81 3.89 4.06 4.26 4.59 ns ns ns ns ns fclk delay (corner pad): or3t20 or3t30 or3t55 or3c/t80 or3t125 fclkc_del 10.34 11.01 7.88 8.11 8.60 9.15 10.07 6.41 6.58 6.95 7.34 7.96 5.40 5.58 5.94 6.33 6.94 ns ns ns ns ns select devices have been discontinued. see ordering information section for product status.
122 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 53 . general-purpose clock timing characteristics (internally generated clock) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. notes: this table represents the delay for an internally generated clock from the clock tree input in one of the four middle pics (using psw routing) on any side of the device which is then distributed to the pfu/pio clock inputs. if the clock tree input used is located at any other pic, see the results reported by isplever. this clock delay is for a fully routed clock tree that uses the general clock network. the delay will be reduced if any of the clock branches are not used. see pin-to-pin timing in table 56 for clock delays of clocks input on general i/o pins. device (t j = 85 ?, v dd = min) symbol speed unit -4 -5 -6 -7 min max min max min max min max or3t20 clk_del 4.22 3.46 2.84 ns or3t30 clk_del 4.29 3.48 2.87 ns or3t55 clk_del 5.34 4.41 3.53 2.93 ns or3c/t80 clk_del 5.49 4.52 3.57 2.98 ns or3t125 clk_del 4.80 3.71 3.13 ns select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 123 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 54. or3cxx expressclk to output delay (pin-to-pin) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?; c l = 50 pf. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?;c l = 50 pf. notes: timing is without the use of the programmable clock manager (pcm). this clock delay is for a fully routed clock tree that uses the expressclk network. it includes both the input buffer delay, the clock routing to the pio clk input, the clock q of the ff, and the delay through the output buffer. the given timing requires that the input clock pin be located at one of the six expressclk inputs of the device, and that a pio ff be used. 5-4846(f).a figure 76. expressclk to output delay description (t j = 85 ?, v dd = min) device speed unit -4 -5 -6 -7 min max min max min max min max eclk middle input pin output pin (fast) or3t20 or3t30 or3t55 or3c/t80 or3t125 9.93 10.10 7.78 7.84 7.96 8.08 8.28 5.40 5.43 5.48 5.54 5.64 4.38 4.40 4.44 4.49 4.58 ns ns ns ns ns eclk middle input pin output pin (slewlim) or3t20 or3t30 or3t55 or3c/t80 or3t125 12.37 12.54 9.77 9.83 9.95 10.07 10.27 6.07 6.10 6.15 6.21 6.31 4.91 4.93 4.97 5.02 5.11 ns ns ns ns ns eclk middle input pin output pin (sinklim) or3t20 or3t30 or3t55 or3c/t80 or3t125 13.73 13.90 11.12 11.18 11.30 11.42 11.62 10.92 10.95 11.00 11.06 11.16 9.65 9.67 9.71 9.76 9.85 ns ns ns ns ns additional delay if eclk corner pin used or3t20 or3t30 or3t55 or3c/t80 or3t125 1.97 1.97 1.91 1.91 1.91 1.91 1.90 1.80 1.90 2.09 2.28 2.57 1.58 1.67 1.84 2.02 2.29 ns ns ns ns ns output (50 pf load) qd eclk eclk pio ff clkcntrl select devices have been discontinued. see ordering information section for product status.
124 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 55 . or3cxx fast clock (fclk) to output delay (pin-to-pin) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?; c l = 50 pf. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?; c l = 50 pf. notes: timing is without the use of the programmable clock manager (pcm). this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay, the clock routing to the pio clk input, the clock q of the ff, and the delay through the output buffer. the delay will be reduced if any of the clock branches are not used. the given timing requires that the input clock pin be located at one of the six expressclk inputs of the device and that a pio ff be used. 5-4846(f).b figure 77. fast clock to output delay description (t j = 85 ?, v dd = min) device speed unit -4 -5 -6 -7 min max min max min max min max output not on same side of device as input clock (fast clock delays using expressclk inputs) eclk middle input pin output pin (fast) or3t20 or3t30 or3t55 or3c/t80 or3t125 14.68 15.30 11.13 11.35 11.81 12.33 13.20 7.94 8.01 8.18 8.36 8.68 6.40 6.48 6.66 6.85 7.19 ns ns ns ns ns eclk middle input pin output pin (slewlim) or3t20 or3t30 or3t55 or3c/t80 or3t125 17.11 17.74 13.12 13.33 13.80 14.32 15.19 8.61 8.68 8.85 9.04 9.35 6.93 7.01 7.19 7.38 7.72 ns ns ns ns ns eclk middle input pin output pin (sinklim) or3t20 or3t30 or3t55 or3c/t80 or3t125 18.47 19.10 14.47 14.68 15.15 15.67 16.54 13.46 13.53 13.70 13.88 14.20 11.67 11.75 11.93 12.12 12.46 ns ns ns ns ns additional delay if eclk corner pin used or3t20 or3t30 or3t55 or3c/t80 or3t125 2.10 2.14 1.97 1.99 2.01 2.04 2.09 1.82 1.92 2.12 2.33 2.63 1.60 1.69 1.88 2.07 2.39 ns ns ns ns ns output (50 pf load) qd eclk fclk pio ff clkcntrl select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 125 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 56 . or3cxx general system clock (sclk) to output delay (pin-to-pin) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?; c l = 50 pf. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?; c l = 50 pf. note: this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay, the clock routing to the pio clk input, the clock q of the ff, and the delay through the output buffer. the delay will be reduced if any of the clock branches are not used. the given timing requires that the input clock pin be located at one of the four center pics on any side of the device and that a pio ff be used. for clock pins located at any other pio, see the results reported by isplever. 5-4846(f) figure 78. system clock to output delay description (t j = 85 ?, v dd = min) device speed unit -4 -5 -6 -7 min max min max min max min max output on same side of device as input clock (system clock delays using general user i/o inputs) clock input pin (mid-pic) output pin (fast) or3t20 or3t30 or3t55 or3c/t80 or3t125 14.91 15.71 11.35 11.63 12.17 12.80 13.69 7.74 7.93 8.28 8.66 9.24 6.10 6.27 6.59 6.95 7.49 ns ns ns ns ns clock input pin (mid-pic) output pin (slewlim) or3t20 or3t30 or3t55 or3c/t80 or3t125 17.34 18.14 13.34 13.62 14.16 14.79 15.68 8.42 8.60 8.95 9.34 9.91 6.63 6.80 7.12 7.48 8.02 ns ns ns ns ns clock input pin (mid-pic) output pin (sinklim) or3t20 or3t30 or3t55 or3c/t80 or3t125 18.70 19.51 14.69 14.97 15.51 16.14 17.03 13.26 13.45 13.80 14.18 14.76 11.37 11.54 11.86 12.22 12.76 ns ns ns ns ns additional delay if non-mid-pic used as clock pin or3t20 or3t30 or3t55 or3c/t80 or3t125 0.41 0.63 0.16 0.20 0.36 0.55 1.11 0.18 0.21 0.37 0.57 1.05 0.17 0.20 0.35 0.55 1.02 ns ns ns ns ns output not on same side of device as input clock (system clock delays using general user i/o inputs) additional delay if output not on same side as input clock pin or3t20 or3t30 or3t55 or3c/t80 or3t125 0.41 0.63 0.16 0.20 0.36 0.55 1.11 0.18 0.21 0.37 0.57 1.05 0.17 0.20 0.35 0.55 1.02 ns ns ns ns ns output (50 pf load) qd sclk pio ff select devices have been discontinued. see ordering information section for product status.
126 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 57 . or3c/txxx input to expressclk (eclk) fast-capture setup/hold time (pin-to-pin) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. note: the pin-to-pin timing parameters in this table should be used instead of results reported by isplever. the eclk delays are to all of the pios on one side of the device for middle pin input, or two sides of the device for corner pin input. the delay includes both the input buffer delay and the clock routing to the pio clock input. description (t j = 85 ?, v dd = min) device speed unit -4 -5 -6 -7 min max min max min max min max input to eclk setup time (middle eclk pin) or3t20 or3t30 or3t55 or3c/t80 or3t125 1.36 1.25 1.34 1.30 1.22 1.14 1.03 0.88 0.86 0.83 0.80 0.76 0.83 0.82 0.80 0.77 0.74 ns ns ns ns ns input to eclk setup time (middle eclk pin, delayed data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 6.91 6.79 6.30 6.27 6.19 6.11 6.00 5.32 5.30 5.27 5.24 5.20 5.98 5.97 5.95 5.93 5.90 ns ns ns ns ns input to eclk setup time (corner eclk pin) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to eclk setup time (corner eclk pin, delayed data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 4.94 4.82 4.39 4.35 4.28 4.21 4.10 3.51 3.40 3.18 2.98 2.63 4.41 4.31 4.11 3.91 3.61 ns ns ns ns ns input to eclk hold time (middle eclk pin) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to eclk hold time (middle eclk pin, delayed data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 127 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 57 . or3c/txxx input to expressclk (eclk) fast-capture setup/hold time (pin-to-pin) (continued) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. notes: the pin-to-pin timing parameters in this table should be used instead of results reported by isplever. the eclk delays are to all of the pios on one side of the device for middle pin input, or two sides of the device for corner pin input. the delay includes both the input buffer delay and the clock routing to the pio clock input. 5-4847(f).b figure 79. input to expressclk setup/hold time description (t j = 85 ?, v dd = min) device speed unit -4 -5 -6 -7 min max min max min max min max input to eclk hold time (corner eclk pin) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.80 0.00 0.00 0.00 0.00 1.10 0.00 0.00 ns ns ns ns ns input to eclk hold time (corner eclk pin, delayed data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns qd clk input pio eclk latch clkcntrl eclk select devices have been discontinued. see ordering information section for product status.
128 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 58. or3c/txxx input to fast clock setup/hold time (pin-to-pin) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. notes: the pin-to-pin timing parameters in this table should be used instead of results reported by isplever. the fclk delays are for a fully routed clock tree that uses the expressclk input into the fast clock network. it includes both the input buffer delay and the clock routing to the pfu clk input. the delay will be reduced if any of the clock branches are not used. description (t j = 85 ?, v dd = min) device speed unit -4 -5 -6 -7 min max min max min max min max output not on same side of device as input clock (fast clock delays using expressclk inputs) input to fclk setup time (middle eclk pin) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to fclk setup time (middle eclk pin, delayed data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.29 0.14 0.80 0.74 0.62 0.50 0.22 0.58 0.55 0.51 0.46 0.33 2.20 2.17 2.11 2.06 1.90 ns ns ns ns ns input to fclk setup time (corner eclk pin) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to fclk setup time (corner eclk pin, delayed data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to fclk hold time (middle eclk pin) or3t20 or3t30 or3t55 or3c/t80 or3t125 6.33 6.95 4.29 4.50 4.97 5.49 6.36 3.72 3.80 3.96 4.15 4.47 3.27 3.35 3.52 3.72 4.05 ns ns ns ns ns select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 129 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 58. or3c/txxx input to fast clock setup/hold time (pin-to-pin) (continued) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. notes: the pin-to-pin timing parameters in this table should be used instead of results reported by isplever. the fclk delays are for a fully routed clock tree that uses the expressclk input into the fast clock network. it includes both the input buffer delay and the clock routing to the pfu clk input. the delay will be reduced if any of the clock branches are not used. 5-4847(f).a figure 80. input to fast clock setup/hold time description (t j = 85 ?, v dd = min) device speed unit -4 -5 -6 -7 min max min max min max min max input to fclk hold time (middle eclk pin, delayed data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to fclk hold time (corner eclk pin) or3t20 or3t30 or3t55 or3c/t80 or3t125 8.43 9.09 6.26 6.49 6.98 7.53 8.45 5.54 5.72 6.09 6.47 7.10 4.88 5.04 5.40 5.79 6.40 ns ns ns ns ns input to fclk hold time (corner eclk pin, delayed data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns qd eclk input pio ff clkcntrl fclk select devices have been discontinued. see ordering information section for product status.
130 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 59. or3c/txxx input to general system clock (sclk) setup/hold time (pin-to-pin) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. notes: the pin-to-pin timing parameters in this table should be used instead of results reported by isplever. this clock delay is for a fully routed clock tree that uses the clock network. it includes both the input buffer delay and the clock routing to the pio ff clk input. the delay will be reduced if any of the clock branches are not used. the given setup (delayed and no delay) and hold (delayed) timing allows the input clock pin to be located in any pio on any side of the device, but a pio ff must be used. the hold (no delay) timing assumes the clock pin is located at one of the four middle pics on any side of the device and that a pio ff is used. if the clock pin is located elsewhere, then the last parameter in the table must be added to the hold (no delay) timing. 5-4847(f) figure 81. input to system clock setup/hold time description (t j = 85 ?, v dd = min) device speed unit -4 -5 -6 -7 min max min max min max min max input to sclk setup time or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to sclk setup time (delayed data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.99 0.79 1.33 1.22 1.09 0.93 0.78 1.47 1.40 1.33 1.26 1.19 3.09 3.03 2.97 2.91 2.86 ns ns ns ns ns input to sclk hold time or3t20 or3t30 or3t55 or3c/t80 or3t125 6.82 7.62 4.74 5.01 5.56 6.19 7.07 3.64 3.83 4.18 4.56 5.14 3.04 3.22 3.54 3.89 4.44 ns ns ns ns ns input to sclk hold time (delayed data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns additional hold time if non- mid-pic used as sclk pin (no delay on data input) or3t20 or3t30 or3t55 or3c/t80 or3t125 0.41 0.63 0.16 0.20 0.36 0.55 1.11 0.18 0.21 0.37 0.57 1.05 0.17 0.20 0.35 0.55 1.02 ns ns ns ns ns qd sclk input pio ff select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 131 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) con?uration timing table 60. general con?uration mode timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. * not applicable to asynchronous peripheral mode. parameter symbol min max unit all con?uration modes m[3:0] setup time to init high tsmode 0.00 ns m[3:0] hold time from init high thmode 600.00 ns reset pulse width low to start recon?uration trw 50.00 ns prgm pulse width low to start recon?uration tpgw 50.00 ns master and asynchronous peripheral modes power-on reset delay cclk period (m3 = 0) (m3 = 1) con?uration latency (autoincrement mode): or3t20 (m3 = 0) (m3 = 1) or3t30 (m3 = 0) (m3 = 1) or3t55 (m3 = 0) (m3 = 1) or3c/t80 (m3 = 0) (m3 = 1) or3t125 (m3 = 0) (m3 = 1) tpo tcclk tcl 15.70 60.00 480.00 11.50 92.10 15.10 121.00 23.20 185.00 33.70 270.00 52.30 418.00 52.40 200.00 1600.00 38.40* 307.00* 50.40* 403.30* 77.40* 619.00* 113.00* 900.00* 175.00* 1395.00* ms ns ns ms ms ms ms ms ms ms ms ms ms microprocessor (mpi) mode power-on reset delay con?uration latency (autoincrement mode): or3t20 or3t30 or3t55 or3c/t80 or3t125 tpo tcl 15.70 27413 35445 53341 76317 116581 52.40 ms write cycles write cycles write cycles write cycles write cycles partial reconguration (explicit mode): or3t20 or3t30 or3t55 or3c/t80 or3t125 tpr 32 36 43 51 62 write cycles write cycles write cycles write cycles write cycles slave serial mode power-on reset delay cclk period or3cxx or3txxx con?uration latency (autoincrement mode): or3t20 or3t30 or3t55 or3c80 or3t80 or3t125 tpo tcclk tcl 3.90 40 15 2.80 3.80 5.80 22.50 8.40 13.09 13.10 ms ns ns ms ms ms ms ms ms select devices have been discontinued. see ordering information section for product status.
132 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 60. general configuration mode timing characteristics (continued) or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. note: t po is triggered when v dd reaches between 3.0 v to 4.0 v for the or3cxx and between 2.7 v and 3.0 v for the or3txxx. parameter symbol min max unit slave parallel mode power-on reset delay cclk period: or3cxx or3txxx con?uration latency (normal mode): or3t20 or3t30 or3t55 or3c80 or3t80 or3t125 t po t cclk t cl 3.90 40.00 15.00 0.36 0.47 0.72 2.81 1.05 1.64 13.10 ms ns ns ms ms ms ms ms ms partial recon?uration (explicit mode): or3t20 or3t30 or3t55 or3c80 or3t80 or3t125 t pr 0.48 0.54 0.65 2.04 0.77 0.93 ?/frame ?/frame ?/frame ?/frame ?/frame ?/frame init timing init high to cclk delay: slave parallel slave serial master serial: (m3 = 1) (m3 = 0) master parallel: (m3 = 1) (m3 = 0) t init_cclk 1.00 1.00 1.00 0.50 4.80 1.00 3.40 2.00 16.20 3.60 ? ? ? ? ? ? initialization latency ( prgm high to init high): or3t20 or3t30 or3t55 or3c/t80 or3t125 t il 0.21 0.24 0.30 0.36 0.45 0.68 0.79 1.00 1.20 1.50 ms ms ms ms ms init high to wr , asynchronous peripheral t init_wr 2.00 ? select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 133 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) 5-4531(f) figure 82. general con?uration mode timing diagram v dd cclk m[3:0] prgm init t po + t il t il t cclk t smode t hmode t init_clk done t cl t pgw select devices have been discontinued. see ordering information section for product status.
134 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 61 . master serial configuration mode timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. * data gets clocked out from an external serial rom. the clock to data delay of the serial rom must be less than the cclk frequency since the data available out of the serial rom must be setup and waiting to be clocked into the fpga before the next cclk rising edge. note: serial con?uration data is transmitted out on dout on the falling edge of cclk after it is input on din. 5-4532(f) figure 83. master serial con?uration mode timing diagram parameter symbol min max unit din setup time* t s 60.00 ns din hold time t h 0.00 ns cclk frequency (m3 = 0) f c 5.00 16.67 mhz cclk frequency (m3 = 1) f c 0.63 2.08 mhz cclk to dout delay t d 5.00 ns din cclk dout t s t h bit n t d bit n select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 135 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 62 . master parallel configuration mode timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. notes: the rclk period consists of seven cclks for rclk low and one cclk for rclk high. serial data is transmitted out on dout 1.5 cclk cycles after the byte is input on d[7:0]. 5-6764(f) figure 84. master parallel con?uration mode timing diagram parameter symbol min max unit rclk to address valid t av 60.00 ns d[7:0] setup time to rclk high t s 60.00 ns d[7:0] hold time to rclk high t h 0.00 ns rclk low time (m3 = 0) t cl 7.00 7.00 cclk cycles rclk high time (m3 = 0) t ch 1.00 1.00 cclk cycles rclk low time (m3 = 1) t cl 7.00 7.00 cclk cycles rclk high time (m3 = 1) t ch 1.00 1.00 cclk cycles cclk to dout t d 5.00 ns a[17:0] rclk d[7:0] t cl t ch t av cclk dout t h t s byte n byte n + 1 d0 d1 d2 d3 d4 d5 d6 d7 t d select devices have been discontinued. see ordering information section for product status.
136 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 63 . asynchronous peripheral configuration mode timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. * this parameter is valid whether the end of not rdy is determined from the rdy pin or from the d7 pin. notes: serial data is transmitted out on dout on the falling edge of cclk after the byte is input on d[7:0]. d[6:0] timing is the same as the write data portion of the d7 waveform because d[6:0] are not enabled by rd . 5-4533(f) figure 85. asynchronous peripheral con?uration mode timing diagram parameter symbol min max unit wr , cs0 , and cs1 pulse width t wr 50.00 ns d[7:0] setup time: 3cxx 3txxx t s 20.00 10.50 ns ns d[7:0] hold time t h 0.00 ns rdy delay t rdy 40.00 ns rdy low t b 1.00 8.00 cclk periods earliest wr after rdy goes high* t wr2 0.00 ns rd to d7 enable/disable t den 40.00 ns cclk to dout t d 5.00 ns cs1 d7 cclk dout cs0 rdy d0 d1 d2 t b t wr t s t h t rdy wr d7 t d previous byte t wr2 write data d3 t den t den rd select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 137 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 64. slave serial con?uration mode timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. note: serial con?uration data is transmitted out on dout on the falling edge of cclk after it is input on din. 5-4535(f). figure 86. slave serial con?uration mode timing diagram parameter symbol min max unit din setup time: 3cxx 3txxx t s 20.00 10.50 ns ns din hold time t h 0.00 ns cclk high time: 3cxx 3txxx t ch 20.00 7.00 ns ns cclk low time: 3cxx 3txxx t cl 20.00 7.00 ns ns cclk frequency: 3cxx 3txxx f c 25.00 66.00 mhz mhz cclk to dout t d 20.00 ns din cclk dout t d t s t h t cl t ch bit n bit n select devices have been discontinued. see ordering information section for product status.
138 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) table 65. slave parallel con?uration mode timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. note: daisy-chaining of fpgas is not supported in this mode. 5-2848(f) figure 87. slave parallel con?uration mode timing diagram parameter symbol min max unit cs0 , cs1, wr setup time t s1 40.00 ns cs0 , cs1, wr hold time t h1 20.00 ns d[7:0] setup time: 3cxx 3txxx t s2 20.00 7.00 ns ns d[7:0] hold time t h2 0.00 ns cclk high time: 3cxx 3txxx t ch 20.00 7.00 ns ns cclk low time: 3cxx 3txxx t cl 20.00 7.00 ns ns cclk frequency: 3cxx 3txxx f c 25.00 66.00 mhz mhz t s1 t s2 t h2 cs1 cclk d[7:0] cs0 wr t cl t ch t h1 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 139 data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) microprocessor interface (mpi) con?uration timing characteristics for con?uration timing using the mpi, consult table 49. see figures 67 through 74 for mpi timing diagrams. select devices have been discontinued. see ordering information section for product status.
140 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas timing characteristics (continued) readback timing table 66 . readback timing characteristics or3cxx commercial: v dd = 5.0 v ?5%, 0 ? < t a < 70 ?; industrial: v dd = 5.0 v ?10%, ?0 ? < t a < +85 ?. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, ?0 ? < t a < +85 ?. 5-4536(f) figure 88. readback timing diagram parameter symbol min max unit rd_cfg to cclk setup time t s 50.00 ns rd_cfg high width to abort readback t rba 2 cclk cycles cclk low time t cl 40.00 ns cclk high time t ch 40.00 ns cclk frequency f c 12.50 mhz cclk to rd_data delay t d 40.00 ns t d t ch cclk rd_data t s t cl rd_cfg bit 0 bit 1 bit 0 t rba select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 141 data sheet november 2006 orca series 3c and 3t fpgas input/output buffer measurement conditions note: switch to v dd for t plz /t pzl ; switch to gnd for t phz /t pzh . 5-3234(f) figure 89. ac test loads 5-3233.a(f) figure 90. output buffer delays 5-3235(f) figure 91. input buffer delays 50 pf a. load used to measure propagation delay to the output under test to the output under test 50 pf v cc gnd 1 k b. load used to measure rising/falling edges v dd t phh v dd /2 v ss out[i] pa d out 1.5 v 0.0 v t pll pad out[i] ac test loads (shown above) ts[i] out 0.0 v 1.5 v t phh t pll pa d in[i] in 3.0 v v ss v dd /2 v dd pad in in[i] select devices have been discontinued. see ordering information section for product status.
142 142 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas output buffer characteristics or3cxx 5-4634(f) figure 92. sinklim (t j = 25 ?c, v dd = 5.0 v) 5-4636(f) figure 93. slewlim (t j = 25 ?c, v dd = 5.0 v) 5-4638(f) figure 94. fast (t j = 25 ?c, v dd = 5.0 v) 5-4635(c) figure 95. sinklim (t j = 125 ?c, v dd = 4.5 v) 5-4637(f) figure 96. slewlim (t j = 125 ?c, v dd = 4.5 v) 5-4639(f) figure 97. fast (t j = 125 ?c, v dd = 4.5 v) 70 60 50 40 30 20 10 0 output current, i o (ma) 012345 output voltage, v o (v) i ol i oh 250 225 150 100 50 0 output current, i o (ma) 01234 output voltage, v o (v) i ol i oh 5 200 175 125 75 25 250 225 150 100 50 0 output current, i o (ma) 01234 output voltage, v o (v) i ol i oh 5 200 175 125 75 25 50 40 30 20 10 0 output current, i o (ma) 01234 output voltage, v o (v) i ol i oh 5 150 125 100 75 50 0 output current, i o (ma) 01 2 3 4 output voltage, v o (v) i ol i oh 25 175 125 100 75 50 0 output current, i o (ma) 01 2 3 4 output voltage, v o (v) i ol i oh 25 150 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 143 data sheet november 2006 orca series 3c and 3t fpgas output buffer characteristics (continued) or3txxx 5-6865(f) figure 98. sinklim (t j = 25 ?c, v dd = 3.3 v) 5-6967(f) figure 99. slewlim (t j = 25 ?c, v dd = 3.3 v) 5-6867(f) figure 100. fast (t j = 25 ?c, v dd = 3.3 v) 5-6866(f) figure 101. sinklim (t j = 125 ?c, v dd = 3.0 v) 5-6868(f) figure 102. slewlim (t j = 125 ?c, v dd = 3.0 v) 5-6868(f) figure 103. fast (t j = 125 ?c, v dd = 3.0 v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 20 40 60 110 output voltage, v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 140 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 140 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 output voltage, v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 80 90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 select devices have been discontinued. see ordering information section for product status.
144 144 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas estimating power dissipation or3cxx the total operating power dissipated is estimated by summing the standby (i ddsb ), internal, and external power dissipated. the internal and external power is the power consumed in the plcs and pics, respec- tively. in general, the standby power is small and may be neglected. the total operating power is as follows: p t = p plc + p pic the internal operating power is made up of two parts: clock generation and pfu output power. the pfu out- put power can be estimated based upon the number of pfu outputs switching when driving an average fan-out of two: p pfu = 0.136 mw/mhz for each pfu output that switches, 0.136 mw/mhz needs to be multiplied times the frequency (in mhz) that the output switches. generally, this can be esti- mated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. the power dissipated by the clock generation circuitry is based upon four parts: the ?ed clock power, the power/clock branch row or column, the clock power dis- sipated in each pfu that uses this particular clock, and the power from the subset of those pfus that are con- ?ured as synchronous memory. therefore, the clock power can be calculated for the four parts using the fol- lowing equations: or3c80 clock power p = [0.224 mw/mhz + (0.288 mw/mhz/branch) (# branches) + (0.033 mw/mhz/pfu) (# pfus) + (0.008 mw/mhz/pio (# pios)] for a quick estimate, the worst-case (typical circuit) or3c80 clock power 21.06 mw/mhz. the power dissipated in a pic is the sum of the power dissipated in the four pios in the pic. this consists of power dissipated by inputs and ac power dissipated by outputs. the power dissipated in each pio depends on whether it is con?ured as an input, output, or input/ output. if a pio is operating as an output, then there is a power dissipation component for p in , as well as p out . this is because the output feeds back to the input. the power dissipated by a ttl input buffer is estimated as: p ttl = 2.2 mw + 0.17 mw/mhz the power dissipated by an input buffer is estimated as: p cmos = 0.17 mw/mhz the ac power dissipation from an output or bidirec- tional is estimated by the following: p out = (c l + 8.8 pf) x v dd 2 x f watts where the unit for c l is farads, and the unit for f is hz. as an example of estimating power dissipation, sup- pose that a fully utilized or3c80 has an average of six outputs for each of the 484 pfus, that 10 clock brances are used so that the clock is driven to the entire plc array, that 150 of the 484 pfus have ffs clocked at 40 mhz, and that the pfuoutputs have an average activity factor of 20%. twenty ttl-con?ured inputs, 20 cmos-con?ured inputs, 32 outputs driving 30 pf loads, and 16 biderec- tional i/os driving 50 pf loads are also generated from the 40 mhz clock with an average activity factor of 20%. all of the ouptut pios are registered, and 30 of the input pios are registered. the worst-case (v dd = 5.25 v) power dissipation is estimated as follows: p pfu = 484 x 6 (0.136 mw/mhz x 20 mhz x 20%) = 1579.78 mw p clk = [40 x [0.224 mw/mhz + (0.288 mw/mhz/branch) (10 branches) + (0.033 mw/mhz/pfu) (150 pfus) + (0.008 mw/mhz/pio) (58 pios)] = 340.72 mw p ttl = 20 x [2.2 mw + (0.17 mw/mhz x 20 mhz x 20%)] = 57.6 mw p cmos = 20 x [0.17 mw x 20 mhz x 20%] = 13.6 mw p out = 32 x [(30 pf + 8.8 pf) x (5.25) 2 x 20 mhz x 20%] = 136.89 mw p bid = 16 x [(50 pf + 8.8 pf) x (5.25) 2 x 20 mhz x 20%] = 103.72 mw total = 2.23 w select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 145 data sheet november 2006 orca series 3c and 3t fpgas estimating power dissipation (continued) or3txxx the total operating power dissipated is estimated by summing the standby (i ddsb ), internal, and external power dissipated. the internal and external power is the power consumed in the plcs and pics, respec- tively. in general, the standby power is small and may be neglected. the total operating power is as follows: p t = p plc + p pic the internal operating power is made up of two parts: clock generation and pfu output power. the pfu out- put power can be estimated based upon the number of pfu outputs switching when driving an average fan-out of two: p pfu = 0.068 mw/mhz for each pfu output that switches, 0.068 mw/mhz needs to be multiplied times the frequency (in mhz) that the output switches. generally, this can be esti- mated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. the power dissipated by the clock generation circuitry is based upon four parts: the ?ed clock power, the power/clock branch row or column, the clock power dis- sipated in each pfu that uses this particular clock, and the power from the subset of those pfus con?ured as synchronous memory. therefore, the clock power can be calculated for the four parts using the following equations. or3t20 clock power p = [0.38 mw/mhz + (0.045 mw/mhz/branch) (# branches) + (0.015 mw/mhz/pfu) (# pfus) + (0.004 mw/mhz/pio (# pios)] for a quick estimate, the worst-case (typical circuit) or3t20 clock power 2.92 mw/mhz. or3t30 clock power p = [0.53 mw/mhz + (0.061 mw/mhz/branch) (# branches) + (0.015 mw/mhz/pfu) (# pfus) + (0.004 mw/mhz/pio (# pios)] for a quick estimate, the worst-case (typical circuit) or3t30 clock power 3.98 mw/mhz. or3t55 clock power p = [0.88 mw/mhz + (0.102 mw/mhz/branch) (# branches) + (0.015 mw/mhz/pfu) (# pfus) + (0.004 mw/mhz/pio (# pios)] for a quick estimate, the worst-case (typical circuit) or3t55 clock power 6.58 mw/mhz. or3t80 clock power p = [0.107 mw/mhz + (0.124 mw/mhz/branch) (# branches) + (0.015 mw/mhz/pfu) (# pfus) + (0.004 mw/mhz/pio (# pios)] for a quick estimate, the worst-case (typical circuit) or3t80 clock power 9.47 mw/mhz. or3t125 clock power p = [0.167 mw/mhz + (0.193 mw/mhz/branch) (# branches) + (0.015 mw/mhz/pfu) (# pfus) + (0.004 mw/mhz/pio (# pios)] for a quick estimate, the worst-case (typical circuit) or3t125 clock power 15.44 mw/mhz. the power dissipated in a pic is the sum of the power dissipated in the four pios in the pic. this consists of power dissipated by inputs and ac power dissipated by outputs. the power dissipated in each pio depends on whether it is con?ured as an input, output, or input/ output. if a pio is operating as an output, then there is a power dissipation component for p in , as well as p out . this is because the output feeds back to the input. the power dissipated by an input buffer (v ih = v dd ? 0.3 v or higher) is estimated as: p in = 0.09 mw/mhz the ac power dissipation from an output or bidirec- tional is estimated by the following: p out = (c l + 8.8 pf) x v dd 2 x f watts where the unit for c l is farads, and the unit for f is hz. select devices have been discontinued. see ordering information section for product status.
146 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas estimating power dissipation (continued) as an example of estimating power dissipation, suppose that a fully utilized or3t80 has an average of six outputs for each of the 484 pfus, that 12 clock branches are used so that the clock is driven to the entire plc array, that 250 of the 484 pfus have ffs clocked at 40 mhz, and that the pfu outputs have an average activity factor of 20%. eighty inputs, 40 of them used as 5 v tolerant inputs, 50 outputs driving 30 pf loads, and 30 bidirectional i/os driving 50 pf loads are also generated from the 40 mhz clock with an average activity factor of 20%. all of the output pios are registered, and 30 of the input pios are registered. the worst-case (v dd = 3.6 v) power dissipation is estimated as follows: p pfu = 484 x 6 (0.068 mw/mhz x 20 mhz x 20%) = 789.9 mw p clk = [0.107 mw/mhz + (0.09 mw/mhz ?branch) (12 branches) + (0.015 mw/mhz ?pfu) (250 pfus) + (0.004 mw/mhz/pio) (110 pios)] = 230.43 mw p in = 80 x [0.09 mw/mhz x 20 mhz x 20%] = 28.8 mw p out = 50 x [(30 pf + 8.8 pf) x (3.6) 2 x 20 mhz x 20%] = 100.57 mw p bid = 30 x [(50 pf + 8.8 pf) x (3.6) 2 x 20 mhz x 20%] = 91.45 mw total = 1.241 w select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 147 data sheet november 2006 orca series 3c and 3t fpgas pin information pin descriptions this section describes the pins found on the series 3 fpgas. any pin not described in this table is a user-program- mable i/o. during con?uration, the user-programmable i/os are 3-stated with an internal pull-up resistor enabled. if any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled after con?uration. table 67. pin descriptions symbol i/o description dedicated pins v dd positive power supply. gnd ground supply. v dd 5 5 v tolerant select. v dd 5 pin locations are shown for package compatibility with or2txxa devices. connections to 5 v power sources are not used for 5 v tolerant i/os in the or3txxx devices. reset i during con?uration, reset forces the restart of con?uration and a pull-up is enabled. after con?uration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk i in the master and asynchronous peripheral modes, cclk is an output which strobes con?uration data in. in the slave or synchronous peripheral mode, cclk is input synchronous with the data on din or d[7:0]. in microprocessor mode, cclk is used internally and output for daisy-chain operation. done i o as an input, a low level on done delays fpga start-up after con?uration (see note). as an active-high, open-drain output, a high level on this signal indicates that con?- uration is complete. done has an optional pull-up resistor. prgm i prgm is an active-low input that forces the restart of con?uration and resets the boundary-scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during con?uration, rd_cfg is an active-low input that activates the ts_all func- tion and 3-states all of the i/o. after con?uration, rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the con?uration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides con- ?uration data out. if used in boundary scan, tdo is test data out. special-purpose pins m0, m1, m2 i i/o during powerup and initialization, m0?2 are used to select the con?uration mode with their values latched on the rising edge of init ; see table 34 for the con?- uration modes. during con?uration, a pull-up is enabled. after con?uration, these pins are user-programmable i/o (see note). note: the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con?uration pins (and the activation of all user i/os) is controlled by a second set of options. select devices have been discontinued. see ordering information section for product status.
148 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas pin information (continued) table 67. pin descriptions (continued) symbol i/o description special-purpose pins (continued) m3 i i/o during powerup and initialization, m3 is used to select the speed of the internal oscillator dur- ing con?uration with their values latched on the rising edge of init . when m3 is low, the oscil- lator frequency is 10 mhz. when m3 is high, the oscillator is 1.25 mhz. during con?uration, a pull-up is enabled. after con?uration, this pin is a user-programmable i/o pin (see note). tdi, tck, tms i i/o if boundary scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary scan is not selected, all boundary-scan functions are inhibited once con?uration is complete. even if boundary scan is not used, either tck or tms must be held at logic 1 dur- ing con?uration. each pin has a pull-up enabled during con?uration. after con?uration, these pins are user-programmable i/o (see note). rdy/rclk/ mpi_ale o o i i/o during con?uration in peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. during the master parallel con?uration mode, rclk is a read output signal to an external memory. this output is not normally used. in i960 microprocessor mode, this pin acts as the address latch enable (ale) input. after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin (see note). hdc o i/o high during con?uration is output high until con?uration is complete. it is used as a control output, indicating that con?uration is not complete. after con?uration, this pin is a user-programmable i/o pin (see note). ldc o i/o lo w dur ing con gur ation is output low until con?uration is complete. it is used as a control out- put, indicating that con?uration is not complete. after con?uration, this pin is a user-programmable i/o pin (see note). init i/o i/o init is a bidirectional signal before and during con?uration. during con?uration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain out- put, init is held low during power stabilization and internal clearing of memory. as an active- low input, init holds the fpga in the wait-state before the start of con?uration. after con?uration, this pin is a user-programmable i/o pin (see note). note: the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con?uration pins (and the activation of all user i/os) is controlled by a second set of options. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 149 data sheet november 2006 orca series 3c and 3t fpgas special-purpose pins (continued) cs0 , cs1 i i/o cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and microprocessor con?uration modes. the fpga is selected when cs0 is low and cs1 is high. during con?- uration, a pull-up is enabled. after con?uration, these pins are user-programmable i/o pins (see note). rd / mpi_strb i i i/o rd is used in the asynchronous peripheral con?uration mode. a low on rd changes d7 into a status output. as a status indication, a high indicates ready, and a low indicates busy. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the microprocessor interface ( mpi ) data transfer strobe. for powerpc , it is the transfer start (ts). for i960 , it is the address/data strobe ( ads ). after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin (see note). wr i i/o wr is used in the asynchronous peripheral con?uration mode. when the fpga is selected, a low on the write strobe, wr , loads the data on d[7:0] inputs into an internal data buffer. wr and rd should not be used simultaneously. if they are, the write strobe overrides. after con?uration, this pin is a user-programmable i/o pin (see note). a[17:0] o i/o during master parallel con?uration mode, a[17:0] address the con?uration eprom. in microprocessor interface ( mpi ) mode, many of the a[n] pins have alternate uses as described below. see the special function blocks section for more mpi information. during con?ura- tion, if not in master parallel or an mpi con?uration mode, these pins are 3-stated with a pull- up enabled. after con?uration, the pins are user-programmable i/o pins (see note). pin information (continued) table 67. pin descriptions (continued) symbol i/o description note: the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con?uration pins (and the activation of all user i/os) is controlled by a second set of options. select devices have been discontinued. see ordering information section for product status.
150 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas special-purpose pins (continued) a11/ mpi_irq o i/o mpi active-low interrupt request output. after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin (see note). a10/ mpi_bi o i/o powerpc mode mpi burst inhibit output. after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin (see note). a9/ mpi_a ck o i/o in powerpc mode mpi operation, this is the active-high transfer acknowledge ( t a ) output. for i960 mpi operation, it is the active-low ready/record ( rd yrcv ) output. after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin (see note). a8/mpi_rw i i/o in powerpc mode mpi operation, this is the active-low write/active-high read control signals. for i960 operation, it is the active-high write/active-low read control signal. after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin (see note). a7/mpi_clk i i/o this is the clock used for the synchronous mpi interface. for powerpc , it is the clkout signal. for i960 , it is the system clock that is chosen for the i960 external bus interface. after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin (see note). a[4:0] i i/o for powerpc operation, these are the powerpc address inputs. the address bit mapping (in powerpc /fpga notation) is a[31]/a[0], a[30]/a[1], a[29]/a[2], a[28]/a[3], a[27]/a[4]. note that a[27]/a[4] is the msb of the address. the a[4:2] inputs are not used in i960 mpi mode. after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin (see note). a[1:0]/ mpi_be[1:0] i i/o for i960 operation, mpi_be[1:0] provide the i960 byte enable signals, be[1:0] , that are used as address bits a[1:0] in i960 byte-wide operation. after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin (see note). d[7:0] i i/o during master parallel, peripheral, and slave parallel con?uration modes, d[7:0] receive con- ?uration data, and each pin has a pull-up enabled. during serial con?uration modes, d0 is the din input. d[7:0] are also the data pins for powerpc microprocessor mode and the address/data pins for i960 microprocessor mode. after con?uration, the pins are user-programmable i/o pins (see note). din i i/o during slave serial or master serial con?uration modes, din accepts serial con?uration data synchronous with cclk. during parallel con?uration modes, din is the d0 input. dur- ing con?uration, a pull-up is enabled. after con?uration, this pin is a user-programmable i/o pin (see note). dout o i/o during con?uration, dout is the serial data output that can drive the din of daisy-chained slave lca devices. data out on dout changes on the falling edge of cclk. after con?uration, dout is a user-programmable i/o pin (see note). pin information (continued) table 67. pin descriptions (continued) symbol i/o description note: the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con?uration pins (and the activation of all user i/os) is controlled by a second set of options. select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 151 data sheet november 2006 orca series 3c and 3t fpgas pin information (continued) package compatibility table 68 provides the number of user i/os available for the orca series 3 fpgas for each available package. each package has six dedicated con?uration pins. tables 70?5 provide the package pin and pin function for the orca series 3 fpgas and packages. the bond pad name is identi?d in the pic nomenclature used in the isplever design editor. when the number of fpga bond pads exceeds the number of package pins, bond pads are unused. when the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). when a package pin is to be left as a no connect for a speci? die, it is indicated as a note in the device pad col- umn for the fpga. the tables provide no information on unused pads. table 68. orca i/os summary *user i/o count includes four expressclk inputs. device 144-pin tqfp 208-pin sqfp/sqpf2 240-pin sqfp/sqfp2 256-pin pbga 352-pin pbga 432-pin ebga or3t20 user i/os* 114 171 192 v dd /v ss 24 31 26 con?uration 6 6 6 unused 0 0 32 or3t30 user i/os* 171 192 221 v dd /v ss ? 14 02 6 con?uration 6 6 6 unused 0 2 3 or3t55 user i/os* 171 192 223 288 v dd /v ss ? 14 22 64 8 con?uration 6 6 6 6 unused 0 0 1 10 or3c/t80 user i/os* 171 192 298 342 v dd /v ss 31 42 48 84 con?uration 6 6 6 6 unused 0 0 0 0 or3t125 user i/os* 171 192 298 342 v dd /v ss 31 42 48 84 con?uration 6 6 6 6 unused 0 0 0 0 select devices have been discontinued. see ordering information section for product status.
152 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas pin information (continued) compatibility with or2c/txxa series the pinouts shown for the or3cxx and or3txxx devices are consistent with the or2c/txxa series for all devices offered in the same packages. this includes the following pins: v dd , v ss , v dd 5 (or2txxa series only), and all con- ?uration pins. the following restrictions apply: 1. there are two con?uration modes supported in the or2c/txxa series that are not supported in series 3: mas- ter parallel down and synchronous peripheral modes. the series 3 fpgas have two new microprocessor inter- face ( mpi ) con?uration modes that are unavailable in the or2c/txxa series. 2. there are four pins?ne per each device side?hat are user i/o in the or2c/txxa series which can only be used as fast dedicated clocks or global inputs in series 3. these pins are also used to drive the expressclk to the i/o ffs on their given side of the device. these four middle expressclk pins should not be used to connect to a programmable clock manager ( pcm ). a corner expressclk input should be used instead (see item 3 below). see table 69 for a list of these pins in each package. 3. there are two other pins that are user i/o in both the or2c/txxa and series 3 but also have optional added functionality. each of these pins drives the expressclks on two sides of the device. they also have fast connec- tivity to the programmable clock manager ( pcm ). see table 69 for a list of these pins in each package. table 69. series 3 expressclk pins pin name/ package 144-pin tqfp 208-pin sqfp/sqfp2 240-pin sqfp/sqfp2 256-pin pbga 352-pin pbga 432-pin ebga i-eckl 15 22 26 k3 n2 r29 i-eckb 55 80 91 w11 ae14 ah16 i-eckr 92 131 152 k18 n23 t2 i-eckt 124 178 207 b11 b14 c15 i/o-seckll 33 49 56 w1 ab4 ag29 i/o-seckur 111 159 184 a19 a25 d5 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 153 data sheet november 2006 orca series 3c and 3t fpgas table 70. or3t20 144-pin tqfp pinout pin or3t20 pad function 1 vdd vdd 2 vss vss 3 pl1a i/o-a0/mpi_be0 4 pl2d i/o 5 pl2a i/o-a1/mpi_be1 6 pl3d i/o-a2 7 pl3a i/o-a3 8 pl4d i/o 9 pl4c i/o 10 pl4a i/o-a4 11 pl5d i/o-a5 12 pl5c i/o 13 pl5a i/o-a6 14 vss vss 15 peckl i-eckl 16 pl6c i/o 17 pl6a i/o-a7/mpi_clk 18 vdd vdd 19 pl7d i/o 20 pl7c i/o 21 pl7a i/o-a8/mpi_rw 22 vss vss 23 pl8d i/o-a9/mpi_a ck 24 pl8a i/o-a10/mpi_bi 25 pl9d i/o 26 pl9c i/o 27 pl9a i/o-a11/mpi_irq 28 pl10d i/o-a12 29 pl10c i/o 30 pl10a i/o-a13 31 pl11a i/o-a14 32 pl12d i/o 33 pl12b i/o-seckll 34 pl12a i/o-a15 35 vss vss 36 pcclk cclk 37 vdd vdd 38 vss vss 39 pb1a i/o-a16 40 pb1d i/o 41 pb2a i/o-a17 42 pb3a i/o select devices have been discontinued. see ordering information section for product status.
154 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas 43 pb3b i/o 44 pb3d i/o 45 vdd vdd 46 pb4a i/o 47 pb4d i/o 48 pb5a i/o 49 pb5c i/o 50 pb5d i/o 51 pb6a i/o 52 pb6c i/o 53 pb6d i/o 54 vss vss 55 peckb i-eckb 56 pb7c i/o 57 pb7d i/o 58 pb8a i/o 59 pb8d i/o 60 pb9a i/o-hdc 61 pb9c i/o 62 pb9d i/o 63 vdd vdd 64 pb10a i/o-ldc 65 pb10c i/o 66 pb10d i/o 67 pb11a i/o-init 68 pb11d i/o 69 pb12a i/o 70 vss vss 71 pdone done 72 vdd vdd 73 vss vss 74 presetn reset 75 pprgmn prgm 76 pr12a i/o-m0 77 pr12d i/o 78 pr11a i/o 79 pr10a i/o-m1 80 pr10c i/o 81 pr10d i/o 82 pr9a i/o-m2 83 pr9b i/o 84 pr9d i/o 85 pr8a i/o-m3 pin or3t20 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 155 data sheet november 2006 orca series 3c and 3t fpgas 86 pr8d i/o 87 vss vss 88 pr7a i/o 89 pr7c i/o 90 pr7d i/o 91 vdd vdd 92 peckr i-eckr 93 pr6c i/o 94 pr6d i/o 95 vss vss 96 pr5a i/o 97 pr5c i/o 98 pr5d i/o 99 pr4a i/o-cs1 100 pr4d i/o 101 pr3a i/o-cs0 102 pr3d i/o 103 pr2a i/o-rd/mpi_strb 104 pr2c i/o 105 pr2d i/o 106 pr1a i/o-wr 107 vss vss 108 prd_cfgn rd_cfg 109 vdd vdd 110 vss vss 111 pt12d i/o-seckur 112 pt12a i/o-rdy/rclk/ mpi_ale 113 pt11d i/o 114 pt11a i/o-d7 115 pt10d i/o 116 pt10c i/o 117 pt10a i/o-d6 118 vdd vdd 119 pt9d i/o 120 pt9a i/o-d5 121 pt8d i/o 122 pt8b i/o 123 pt8a i/o-d4 124 peckt i-eckt 125 pt7c i/o 126 pt7a i/o-d3 127 vss vss 128 pt6d i/o pin or3t20 pad function select devices have been discontinued. see ordering information section for product status.
156 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas 129 pt6c i/o 130 pt6a i/o-d2 131 pt5d i/o-d1 132 pt5c i/o 133 pt5a i/o-d0/din 134 pt4d i/o 135 pt4a i/o-dout 136 vdd vdd 137 pt3d i/o 138 pt3c i/o 139 pt3a i/o-tdi 140 pt2a i/o-tms 141 pt1d i/o 142 pt1a i/o-tck 143 vss vss 144 prd_data rd_data/tdo pin or3t20 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 157 data sheet november 2006 orca series 3c and 3t fpgas table 71. or3t20, or3t30, or3t55, or3c/t80, and or3t125 208-pin sqfp/sqfp2 pinout pin or3t20 pad or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function 1v ss v ss v ss v ss v ss v ss 2v ss v ss v ss v ss v ss v ss 3 pl1d pl1d pl1d pl1d pl1d i/o 4 pl1a pl2d pl2d pl2d pl2d i/o-a0/ mpi_be0 5 pl2d pl3d pl3d pl4d pl4d i/o 6 pl2c pl3c pl3a pl4a pl5d i/o 7 pl2a pl3a pl4a pl5a pl7d i/o-a1/ mpi_be1 8 pl3d pl4d pl5a pl6a pl8a i/o-a2 9 pl3c pl4c pl6d pl7d pl9d i/o 10 pl3b pl4b pl6b pl7b pl9b i/o 11 pl3a pl4a pl6a pl7a pl9a i/o-a3 12 v dd v dd v dd v dd v dd v dd 13 pl4d pl5d pl7d pl8d pl10d i/o 14 pl4c pl5c pl7c pl8a pl10a i/o 15 pl4b pl5b pl7b pl9d pl11d i/o 16 pl4a pl5a pl7a pl9b pl11a i/o-a4 17 pl5d pl6d pl8d pl9a pl12d i/o-a5 18 pl5c pl6c pl8c pl10c pl12a i/o 19 pl5b pl6b pl8b pl10b pl13d i/o 20 pl5a pl6a pl8a pl10a pl13a i/o-a6 21 v ss v ss v ss v ss v ss v ss 22 peckl peckl peckl peckl peckl i-eckl 23 pl6c pl7c pl9c pl11c pl14c i/o 24 pl6b pl7b pl9b pl11b pl14b i/o 25 pl6a pl7a pl9a pl11a pl14a i/o-a7/mpi_clk 26 v dd v dd v dd v dd v dd v dd 27 pl7d pl8d pl10d pl12d pl15d i/o 28 pl7c pl8c pl10c pl12c pl15c i/o 29 pl7b pl8b pl10b pl12b pl15b i/o 30 pl7a pl8a pl10a pl12a pl15a i/o-a8/mpi_rw 31 v ss v ss v ss v ss v ss v ss 32 pl8d pl9d pl11d pl13d pl16d i/o-a9/ mpi_a ck 33 pl8c pl9c pl11c pl13b pl16a i/o 34 pl8b pl9b pl11b pl13a pl17d i/o 35 pl8a pl9a pl11a pl14c pl17a i/o-a10/ mpi_bi 36 pl9d pl10d pl12d pl14b pl18d i/o 37 pl9c pl10c pl12c pl15c pl18a i/o 38 pl9b pl10b pl12b pl15b pl19d i/o 39 pl9a pl10a pl12a pl15a pl19a i/o-a11/ mpi_irq 40 v dd v dd v dd v dd v dd v dd 41 pl10d pl11d pl13d pl16d pl20d i/o-a12 42 pl10c pl11c pl13b pl16b pl20b i/o select devices have been discontinued. see ordering information section for product status.
158 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas 43 pl10b pl11b pl14d pl17d pl21d i/o 44 pl10a pl11a pl14b pl17b pl21b i/o-a13 45 pl11d pl12d pl15d pl18d pl22d i/o 46 pl11a pl12a pl16d pl19d pl24a i/o-a14 47 pl12d pl13d pl17d pl20d pl26d i/o 48 pl12c pl13a pl17a pl21d pl27d i/o 49 pl12b pl14c pl18c pl21a pl27a i/o-seckll 50 pl12a pl14a pl18a pl22a pl28a i/o-a15 51 v ss v ss v ss v ss v ss v ss 52 pcclk pcclk pcclk pcclk pcclk cclk 53 v ss v ss v ss v ss v ss v ss 54 v ss v ss v ss v ss v ss v ss 55 pb1a pb1a pb1a pb1a pb1a i/o-a16 56 pb1b pb1d pb1d pb2a pb2a i/o 57 pb1c pb2a pb2a pb2d pb2d i/o 58 pb1d pb2d pb2d pb3d pb3d i/o 59 pb2a pb3a pb3d pb4d pb4d i/o-a17 60 pb2d pb3d pb4d pb5d pb5d i/o 61 pb3a pb4a pb5b pb6b pb6d i/o 62 pb3b pb4b pb5d pb6d pb7d i/o 63 pb3c pb4c pb6b pb7b pb8d i/o 64 pb3d pb4d pb6d pb7d pb9d i/o 65 v dd v dd v dd v dd v dd v dd 66 pb4a pb5a pb7a pb8a pb10a i/o 67 pb4b pb5b pb7b pb8d pb10d i/o 68 pb4c pb5c pb7c pb9a pb11a i/o 69 pb4d pb5d pb7d pb9c pb11d i/o 70 pb5a pb6a pb8a pb9d pb12a i/o 71 pb5b pb6b pb8b pb10a pb12d i/o 72 pb5c pb6c pb8c pb10b pb13a i/o 73 pb5d pb6d pb8d pb10d pb13d i/o 74 v ss v ss v ss v ss v ss v ss 75 pb6a pb7a pb9a pb11a pb14a i/o 76 pb6b pb7b pb9b pb11b pb14b i/o 77 pb6c pb7c pb9c pb11c pb14c i/o 78 pb6d pb7d pb9d pb11d pb14d i/o 79 v ss v ss v ss v ss v ss v ss 80 peckb peckb peckb peckb peckb i-eckb 81 pb7b pb8b pb10b pb12b pb15b i/o 82 pb7c pb8c pb10c pb12c pb15c i/o 83 pb7d pb8d pb10d pb12d pb15d i/o 84 v ss v ss v ss v ss v ss v ss 85 pb8a pb9a pb11a pb13a pb16a i/o pin or3t20 pad or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 159 data sheet november 2006 orca series 3c and 3t fpgas 86 pb8b pb9b pb11b pb13b pb16d i/o 87 pb8c pb9c pb11c pb13c pb17a i/o 88 pb8d pb9d pb11d pb14a pb17d i/o 89 pb9a pb10a pb12a pb14b pb18a i/o-hdc 90 pb9b pb10b pb12b pb14d pb18d i/o 91 pb9c pb10c pb12c pb15a pb19a i/o 92 pb9d pb10d pb12d pb15d pb19d i/o 93 v dd v dd v dd v dd v dd v dd 94 pb10a pb11a pb13a pb16a pb20a i/o- ldc 95 pb10b pb11d pb13d pb16d pb21d i/o 96 pb10c pb12a pb14a pb17a pb22a i/o 97 pb10d pb12b pb14d pb17d pb23d i/o 98 pb11a pb12c pb15a pb18a pb24a i/o- init 99 pb11c pb12d pb16a pb19a pb25a i/o 100 pb11d pb13a pb17a pb20a pb26a i/o 101 pb12a pb13d pb18a pb21d pb27d i/o 102 pb12d pb14d pb18d pb22d pb28d i/o 103 v ss v ss v ss v ss v ss v ss 104 pdone pdone pdone pdone pdone done 105 v ss v ss v ss v ss v ss v ss 106 presetn presetn presetn presetn presetn reset 107 pprgmn pprgmn pprgmn pprgmn pprgmn prgm 108 pr12a pr14a pr18a pr22a pr28a i/o-m0 109 pr12d pr13a pr18d pr21a pr27a i/o 110 pr11a pr13d pr17b pr20a pr26a i/o 111 pr11b pr12a pr16a pr19a pr25a i/o 112 pr10a pr11a pr15d pr18d pr22d i/o-m1 113 pr10b pr11b pr14a pr17a pr21a i/o 114 pr10c pr11c pr14d pr17d pr21d i/o 115 pr10d pr11d pr13a pr16a pr20a i/o 116 v dd v dd v dd v dd v dd v dd 117 pr9a pr10a pr12a pr15a pr19a i/o-m2 118 pr9b pr10b pr12b pr15d pr19d i/o 119 pr9c pr10c pr12c pr14a pr18a i/o 120 pr9d pr10d pr12d pr14c pr18d i/o 121 pr8a pr9a pr11a pr14d pr17a i/o-m3 122 pr8b pr9b pr11b pr13a pr17d i/o 123 pr8c pr9c pr11c pr13b pr16a i/o 124 pr8d pr9d pr11d pr13d pr16d i/o 125 v ss v ss v ss v ss v ss v ss 126 pr7a pr8a pr10a pr12a pr15a i/o 127 pr7b pr8b pr10b pr12b pr15b i/o pin or3t20 pad or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
160 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas 128 pr7c pr8c pr10c pr12c pr15c i/o 129 pr7d pr8d pr10d pr12d pr15d i/o 130 v dd v dd v dd v dd v dd v dd 131 peckr peckr peckr peckr peckr i-eckr 132 pr6b pr7b pr9b pr11b pr14b i/o 133 pr6c pr7c pr9c pr11c pr14c i/o 134 pr6d pr7d pr9d pr11d pr14d i/o 135 v ss v ss v ss v ss v ss v ss 136 pr5a pr6a pr8a pr10a pr13a i/o 137 pr5b pr6b pr8b pr10c pr13d i/o 138 pr5c pr6c pr8c pr10d pr12a i/o 139 pr5d pr6d pr8d pr9b pr12d i/o 140 pr4a pr5a pr7a pr9c pr11a i/o-cs1 141 pr4b pr5b pr7b pr9d pr11d i/o 142 pr4c pr5c pr7c pr8a pr10a i/o 143 pr4d pr5d pr7d pr8d pr10d i/o 144 v dd v dd v dd v dd v dd v dd 145 pr3a pr4a pr6a pr7a pr9a i/o- cs0 146 pr3b pr4b pr6b pr7b pr9b i/o 147 pr3c pr4c pr5b pr6b pr8b i/o 148 pr3d pr4d pr5d pr6d pr8d i/o 149 pr2a pr3a pr4a pr5a pr7a i/o- rd / mpi_strb 150 pr2c pr3c pr4d pr5d pr5a i/o 151 pr2d pr3d pr3a pr4a pr4a i/o 152 pr1a pr2a pr2a pr3a pr3a i/o-wr 153 pr1c pr2d pr2c pr2a pr2a i/o 154 pr1d pr1a pr1a pr1a pr1a i/o 155 v ss v ss v ss v ss v ss v ss 156 prd_cfgn prd_cfgn prd_cfgn prd_cfgn prd_cfgn rd_cfg 157 v ss v ss v ss v ss v ss v ss 158 v ss v ss v ss v ss v ss v ss 159 pt12d pt14d pt18d pt22d pt28d i/o-seckur 160 pt12a pt13d pt17d pt21a pt27a i/o-rdy/rclk/mpi_ale 161 pt11d pt13a pt16d pt19d pt25d i/o 162 pt11c pt12d pt16a pt19a pt25a i/o 163 pt11a pt12c pt15d pt18d pt24d i/o-d7 164 pt10d pt12a pt14d pt17d pt23d i/o 165 pt10c pt11d pt14a pt17a pt22d i/o 166 pt10b pt11c pt13d pt16d pt21d i/o 167 pt10a pt11b pt13b pt16b pt20d i/o-d6 168 v dd v dd v dd v dd v dd v dd 169 pt9d pt10d pt12d pt15d pt19d i/o 170 pt9c pt10c pt12c pt15b pt19a i/o pin or3t20 pad or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 161 data sheet november 2006 orca series 3c and 3t fpgas 171 pt9b pt10b pt12b pt15a pt18d i/o 172 pt9a pt10a pt12a pt14c pt18a i/o-d5 173 pt8d pt9d pt11d pt14b pt17d i/o 174 pt8c pt9c pt11c pt13d pt17a i/o 175 pt8b pt9b pt11b pt13c pt16d i/o 176 pt8a pt9a pt11a pt13a pt16a i/o-d4 177 v ss v ss v ss v ss v ss v ss 178 peckt peckt peckt peckt peckt i-eckt 179 pt7c pt8c pt10c pt12c pt15c i/o 180 pt7b pt8b pt10b pt12b pt15b i/o 181 pt7a pt8a pt10a pt12a pt15a i/o-d3 182 v ss v ss v ss v ss v ss v ss 183 pt6d pt7d pt9d pt11d pt14d i/o 184 pt6c pt7c pt9c pt11c pt14c i/o 185 pt6b pt7b pt9b pt11b pt14b i/o 186 pt6a pt7a pt9a pt11a pt14a i/o-d2 187 v ss v ss v ss v ss v ss v ss 188 pt5d pt6d pt8d pt10d pt13d i/o-d1 189 pt5c pt6c pt8c pt10b pt13a i/o 190 pt5b pt6b pt8b pt10a pt12d i/o 191 pt5a pt6a pt8a pt9c pt12a i/o-d0/din 192 pt4d pt5d pt7d pt9b pt11d i/o 193 pt4c pt5c pt7c pt8d pt11a i/o 194 pt4b pt5b pt7b pt8c pt10d i/o 195 pt4a pt5a pt7a pt8a pt10a i/o-dout 196 v dd v dd v dd v dd v dd v dd 197 pt3d pt4d pt6d pt7d pt9d i/o 198 pt3c pt4c pt6a pt7a pt8a i/o 199 pt3b pt4b pt5c pt6c pt7a i/o 200 pt3a pt4a pt5a pt6a pt6a i/o-tdi 201 pt2d pt3d pt4a pt5a pt5a i/o 202 pt2a pt3a pt3a pt4a pt4a i/o-tms 203 pt1d pt2d pt2c pt3a pt3a i/o 204 pt1c pt2a pt2a pt2a pt2a i/o 205 pt1b pt1d pt1d pt1d pt1d i/o 206 pt1a pt1a pt1a pt1a pt1a i/o-tck 207 v ss v ss v ss v ss v ss v ss 208 prd_data prd_data prd_data prd_data prd_data rd_data/tdo pin or3t20 pad or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
162 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas table 72. or3t30, or3t55, or3c/t80, and or3t125 240-pin sqfp/sqfp2 pinout pin or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function 1v ss v ss v ss v ss v ss 2v dd v dd v dd v dd v dd 3 pl1d pl1d pl1d pl1d i/o 4 pl1b pl1c pl1c pl1c i/o 5 pl1a pl1b pl1b pl1b i/o 6 pl2d pl2d pl2d pl2d i/o-a0/ mpi_be0 7v ss v ss v ss v ss v ss 8 pl3d pl3d pl4d pl4d i/o 9 pl3c pl3a pl4a pl5d i/o 10 pl3b pl4d pl5d pl6d i/o 11 pl3a pl4a pl5a pl7d i/o-a1/ mpi_be1 12 pl4d pl5a pl6a pl8a i/o-a2 13 pl4c pl6d pl7d pl9d i/o 14 pl4b pl6b pl7b pl9b i/o 15 pl4a pl6a pl7a pl9a i/o-a3 16 v dd v dd v dd v dd v dd 17 pl5d pl7d pl8d pl10d i/o 18 pl5c pl7c pl8a pl10a i/o 19 pl5b pl7b pl9d pl11d i/o 20 pl5a pl7a pl9b pl11a i/o-a4 21 pl6d pl8d pl9a pl12d i/o-a5 22 pl6c pl8c pl10c pl12a i/o 23 pl6b pl8b pl10b pl13d i/o 24 pl6a pl8a pl10a pl13a i/o-a6 25 v ss v ss v ss v ss v ss 26 peckl peckl peckl peckl i-eckl 27 pl7c pl9c pl11c pl14c i/o 28 pl7b pl9b pl11b pl14b i/o 29 pl7a pl9a pl11a pl14a i/o-a7/mpi_clk 30 v dd v dd v dd v dd v dd 31 pl8d pl10d pl12d pl15d i/o 32 pl8c pl10c pl12c pl15c i/o 33 pl8b pl10b pl12b pl15b i/o 34 pl8a pl10a pl12a pl15a i/o-a8/mpi_rw 35 v ss v ss v ss v ss v ss 36 pl9d pl11d pl13d pl16d i/o-a9/ mpi_a ck 37 pl9c pl11c pl13b pl16a i/o 38 pl9b pl11b pl13a pl17d i/o 39 pl9a pl11a pl14c pl17a i/o-a10/ mpi_bi 40 pl10d pl12d pl14b pl18d i/o 41 pl10c pl12c pl15c pl18a i/o select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 163 data sheet november 2006 orca series 3c and 3t fpgas 42 pl10b pl12b pl15b pl19d i/o 43 pl10a pl12a pl15a pl19a i/o-a11/ mpi_irq 44 v dd v dd v dd v dd v dd 45 pl11d pl13d pl16d pl20d i/o-a12 46 pl11c pl13b pl16b pl20b i/o 47 pl11b pl14d pl17d pl21d i/o 48 pl11a pl14b pl17b pl21b i/o-a13 49 pl12d pl14a pl17a pl21a i/o 50 pl12c pl15d pl18d pl22d i/o 51 pl12b pl15b pl18b pl23d i/o 52 pl12a pl16d pl19d pl24a i/o-a14 53 v ss v ss v ss v ss v ss 54 pl13d pl17d pl20d pl26d i/o 55 pl13a pl17a pl21d pl27d i/o 56 pl14c pl18c pl21a pl27a i/o-seckll 57 pl14a pl18a pl22a pl28a i/o-a15 58 v ss v ss v ss v ss v ss 59 pcclk pcclk pcclk pcclk cclk 60 v dd v dd v dd v dd v dd 61 v ss v ss v ss v ss v ss 62 v ss v ss v ss v ss v ss 63 pb1a pb1a pb1a pb1a i/o-a16 64 pb1d pb1d pb2a pb2a i/o 65 pb2a pb2a pb2d pb2d i/o 66 pb2d pb2d pb3d pb3d i/o 67 v ss v ss v ss v ss v ss 68 pb3a pb3d pb4d pb4d i/o-a17 69 pb3b pb4d pb5d pb5d i/o 70 pb3c pb5a pb6a pb6a i/o 71 pb3d pb5b pb6b pb6d i/o 72 pb4a pb5d pb6d pb7d i/o 73 pb4b pb6a pb7a pb8a i/o 74 pb4c pb6b pb7b pb8d i/o 75 pb4d pb6d pb7d pb9d i/o 76 v dd v dd v dd v dd v dd 77 pb5a pb7a pb8a pb10a i/o 78 pb5b pb7b pb8d pb10d i/o 79 pb5c pb7c pb9a pb11a i/o 80 pb5d pb7d pb9c pb11d i/o 81 pb6a pb8a pb9d pb12a i/o 82 pb6b pb8b pb10a pb12d i/o 83 pb6c pb8c pb10b pb13a i/o 84 pb6d pb8d pb10d pb13d i/o pin or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
164 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas 85 v ss v ss v ss v ss v ss 86 pb7a pb9a pb11a pb14a i/o 87 pb7b pb9b pb11b pb14b i/o 88 pb7c pb9c pb11c pb14c i/o 89 pb7d pb9d pb11d pb14d i/o 90 v ss v ss v ss v ss v ss 91 peckb peckb peckb peckb i-eckb 92 pb8b pb10b pb12b pb15b i/o 93 pb8c pb10c pb12c pb15c i/o 94 pb8d pb10d pb12d pb15d i/o 95 v ss v ss v ss v ss v ss 96 pb9a pb11a pb13a pb16a i/o 97 pb9b pb11b pb13b pb16d i/o 98 pb9c pb11c pb13c pb17a i/o 99 pb9d pb11d pb14a pb17d i/o 100 pb10a pb12a pb14b pb18a i/o-hdc 101 pb10b pb12b pb14d pb18d i/o 102 pb10c pb12c pb15a pb19a i/o 103 pb10d pb12d pb15d pb19d i/o 104 v dd v dd v dd v dd v dd 105 pb11a pb13a pb16a pb20a i/o- ldc 106 pb11d pb13d pb16d pb21d i/o 107 pb12a pb14a pb17a pb22a i/o 108 pb12b pb14d pb17d pb23d i/o 109 pb12c pb15a pb18a pb24a i/o- init 110 pb12d pb15d pb18d pb24d i/o 111 pb13a pb16a pb19a pb25a i/o 112 pb13b pb16d pb19d pb25d i/o 113 v ss v ss v ss v ss 114 pb13d pb17a pb20a pb26a i/o 115 pb14a pb17d pb21a pb27a i/o 116 pb14b pb18a pb21d pb27d i/o 117 pb14d pb18d pb22d pb28d i/o 118 v ss v ss v ss v ss v ss 119 pdone pdone pdone pdone done 120 v dd v dd v dd v dd v dd 121 v ss v ss v ss v ss v ss 122 presetn presetn presetn presetn reset 123 pprgmn pprgmn pprgmn pprgmn prgm 124 pr14a pr18a pr22a pr28a i/o-m0 125 pr14d pr18c pr22d pr28d i/o 126 pr13a pr18d pr21a pr27a i/o 127 pr13d pr17b pr20a pr26a i/o pin or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 165 data sheet november 2006 orca series 3c and 3t fpgas 128 v ss v ss v ss v ss v ss 129 pr12a pr16a pr19a pr25a i/o 130 pr12b pr16d pr19d pr24a i/o 131 pr12c pr15a pr18a pr23a i/o 132 pr12d pr15c pr18c pr23d i/o 133 pr11a pr15d pr18d pr22d i/o-m1 134 pr11b pr14a pr17a pr21a i/o 135 pr11c pr14d pr17d pr21d i/o 136 pr11d pr13a pr16a pr20a i/o 137 v dd v dd v dd v dd v dd 138 pr10a pr12a pr15a pr19a i/o-m2 139 pr10b pr12b pr15d pr19d i/o 140 pr10c pr12c pr14a pr18a i/o 141 pr10d pr12d pr14c pr18d i/o 142 pr9a pr11a pr14d pr17a i/o-m3 143 pr9b pr11b pr13a pr17d i/o 144 pr9c pr11c pr13b pr16a i/o 145 pr9d pr11d pr13d pr16d i/o 146 v ss v ss v ss v ss v ss 147 pr8a pr10a pr12a pr15a i/o 148 pr8b pr10b pr12b pr15b i/o 149 pr8c pr10c pr12c pr15c i/o 150 pr8d pr10d pr12d pr15d i/o 151 v dd v dd v dd v dd v dd 152 peckr peckr peckr peckr i-eckr 153 pr7b pr9b pr11b pr14b i/o 154 pr7c pr9c pr11c pr14c i/o 155 pr7d pr9d pr11d pr14d i/o 156 v ss v ss v ss v ss v ss 157 pr6a pr8a pr10a pr13a i/o 158 pr6b pr8b pr10c pr13d i/o 159 pr6c pr8c pr10d pr12a i/o 160 pr6d pr8d pr9b pr12d i/o 161 pr5a pr7a pr9c pr11a i/o-cs1 162 pr5b pr7b pr9d pr11d i/o 163 pr5c pr7c pr8a pr10a i/o 164 pr5d pr7d pr8d pr10d i/o 165 v dd v dd v dd v dd v dd 166 pr4a pr6a pr7a pr9a i/o- cs0 167 pr4b pr6b pr7b pr9b i/o 168 pr4c pr5b pr6b pr8b i/o 169 pr4d pr5d pr6d pr8d i/o 170 pr3a pr4a pr5a pr7a i/o- rd / mpi_strb pin or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
166 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas 171 pr3b pr4b pr5b pr6a i/o 172 pr3c pr4d pr5d pr5a i/o 173 pr3d pr3a pr4a pr4a i/o 174 v ss v ss v ss v ss v ss 175 pr2a pr2a pr3a pr3a i/o- wr 176 pr2d pr2c pr2a pr2a i/o 177 pr1a pr1a pr1a pr1a i/o 178 pr1d pr1d pr1d pr1d i/o 179 v ss v ss v ss v ss v ss 180 prd_cfgn prd_cfgn prd_cfgn prd_cfgn rd_cfg 181 v ss v ss v ss v ss v ss 182 v dd v dd v dd v dd v dd 183 v ss v ss v ss v ss v ss 184 pt14d pt18d pt22d pt28d i/o-seckur 185 pt14c pt18b pt22a pt28a i/o 186 pt14a pt18a pt21d pt27d i/o 187 pt13d pt17d pt21a pt27a i/o-rdy/rclk/mpi_ale 188 v ss v ss v ss v ss 189 pt13b pt16d pt19d pt25d i/o 190 pt13a pt16c pt19c pt25c i/o 191 pt12d pt16a pt19a pt25a i/o 192 pt12c pt15d pt18d pt24d i/o-d7 193 pt12a pt14d pt17d pt23d i/o 194 pt11d pt14a pt17a pt22d i/o 195 pt11c pt13d pt16d pt21d i/o 196 pt11b pt13b pt16b pt20d i/o-d6 197 v dd v dd v dd v dd v dd 198 pt10d pt12d pt15d pt19d i/o 199 pt10c pt12c pt15b pt19a i/o 200 pt10b pt12b pt15a pt18d i/o 201 pt10a pt12a pt14c pt18a i/o-d5 202 pt9d pt11d pt14b pt17d i/o 203 pt9c pt11c pt13d pt17a i/o 204 pt9b pt11b pt13c pt16d i/o 205 pt9a pt11a pt13a pt16a i/o-d4 206 v ss v ss v ss v ss v ss 207 peckt peckt peckt peckt i-eckt 208 pt8c pt10c pt12c pt15c i/o 209 pt8b pt10b pt12b pt15b i/o 210 pt8a pt10a pt12a pt15a i/o-d3 211 v ss v ss v ss v ss v ss 212 pt7d pt9d pt11d pt14d i/o pin or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 167 data sheet november 2006 orca series 3c and 3t fpgas 213 pt7c pt9c pt11c pt14c i/o 214 pt7b pt9b pt11b pt14b i/o 215 pt7a pt9a pt11a pt14a i/o-d2 216 v ss v ss v ss v ss v ss 217 pt6d pt8d pt10d pt13d i/o-d1 218 pt6c pt8c pt10b pt13a i/o 219 pt6b pt8b pt10a pt12d i/o 220 pt6a pt8a pt9c pt12a i/o-d0/din 221 pt5d pt7d pt9b pt11d i/o 222 pt5c pt7c pt8d pt11a i/o 223 pt5b pt7b pt8c pt10d i/o 224 pt5a pt7a pt8a pt10a i/o-dout 225 v dd v dd v dd v dd v dd 226 pt4d pt6d pt7d pt9d i/o 227 pt4c pt6a pt7a pt8a i/o 228 pt4b pt5c pt6c pt7a i/o 229 pt4a pt5a pt6a pt6a i/o-tdi 230 pt3d pt4d pt5d pt5d i/o 231 pt3c pt4a pt5a pt5a i/o 232 pt3b pt3d pt4d pt4d i/o 233 pt3a pt3a pt4a pt4a i/o-tms 234 v ss v ss v ss v ss v ss 235 pt2d pt2c pt3a pt3a i/o 236 pt2a pt2a pt2a pt2a i/o 237 pt1d pt1d pt1d pt1d i/o 238 pt1a pt1a pt1a pt1a i/o-tck 239 v ss v ss v ss v ss v ss 240 prd_data prd_data prd_data prd_data rd_data/tdo pin or3t30 pad or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
168 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas table 73. or3t20, or3t30, and or3t55 256-pin pbga pinout pin or3t20 pad or3t30 pad or3t55 pad function b1 v dd v dd v dd v dd c2 pl1d pl1d pl1d i/o d2 pl1c pl1b pl1c i/o d3 pl1b pl1a pl1b i/o e4 pl1a pl2d pl2d i/o-a0/mpi_be0 c1 pl2c pl2c i/o d1 pl2b pl2b i/o e3 pl2a pl2a i/o e2 pl2d pl3d pl3d i/o e1 pl2c pl3c pl3a i/o f3 pl2b pl3b pl4d i/o g4 pl2a pl3a pl4a i/o-a1/mpi_be1 f2 pl5d i/o f1 pl3d pl4d pl5a i/o-a2 g3 pl3c pl4c pl6d i/o g2 pl3b pl4b pl6b i/o g1 pl3a pl4a pl6a i/o-a3 h3 pl4d pl5d pl7d i/o h2 pl4c pl5c pl7c i/o h1 pl4b pl5b pl7b i/o j4 pl4a pl5a pl7a i/o-a4 j3 pl5d pl6d pl8d i/o-a5 j2 pl5c pl6c pl8c i/o j1 pl5b pl6b pl8b i/o k2 pl5a pl6a pl8a i/o-a6 k3 peckl peckl peckl i-eckl k1 pl6c pl7c pl9c i/o l1 pl6b pl7b pl9b i/o l2 pl6a pl7a pl9a i/o-a7/mpi_clk l3 pl7d pl8d pl10d i/o l4 pl7c pl8c pl10c i/o m1 pl7b pl8b pl10b i/o m2 pl7a pl8a pl10a i/o-a8/mpi_rw m3 pl8d pl9d pl11d i/o-a9/mpi_a ck m4 pl8c pl9c pl11c i/o n1 pl8b pl9b pl11b i/o n2 pl8a pl9a pl11a i/o-a10/mpi_bi n3 pl9d pl10d pl12d i/o p1 pl9c pl10c pl12c i/o p2 pl9b pl10b pl12b i/o r1 pl9a pl10a pl12a i/o-a11/mpi_irq p3 pl10d pl11d pl13d i/o-a12 r2 pl10c pl11c pl13b i/o t1 pl10b pl11b pl14d i/o select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 169 data sheet november 2006 orca series 3c and 3t fpgas p4 pl10a pl11a pl14b i/o-a13 r3 pl11d pl12d pl14a i/o t2 pl11c pl12c pl15d i/o u1 pl11b pl12b pl15b i/o t3 pl11a pl12a pl16d i/o-a14 u2 pl13d pl17d i/o v1 pl12d pl13c pl17c i/o t4 pl12c pl13b pl17b i/o u3 pl13a pl17a i/o v2 pl14d pl18d i/o w1 pl12b pl14c pl18c i/o-seckll v3 pl14b pl18b i/o w2 pl12a pl14a pl18a i/o-a15 y1 pcclk pcclk pcclk cclk w3 nc y2 pb1a pb1a pb1a i/o-a16 w4 pb1c pb1c i/o v4 pb1b pb1d pb1d i/o u5 pb1c pb2a pb2a i/o y3 pb1d pb2b pb2b i/o y4 pb2c pb2c i/o v5 pb2d pb2d i/o w5 pb2a pb3a pb3d i/o-a17 y5 pb2b pb3b pb4d i/o v6 pb2c pb3c pb5a i/o u7 pb2d pb3d pb5b i/o w6 pb3a pb4a pb5d i/o y6 pb3b pb4b pb6a i/o v7 pb3c pb4c pb6b i/o w7 pb3d pb4d pb6d i/o y7 pb4a pb5a pb7a i/o v8 pb4b pb5b pb7b i/o w8 pb4c pb5c pb7c i/o y8 pb4d pb5d pb7d i/o u9 pb5a pb6a pb8a i/o v9 pb5b pb6b pb8b i/o w9 pb5c pb6c pb8c i/o y9 pb5d pb6d pb8d i/o w10 pb6a pb7a pb9a i/o v10 pb6b pb7b pb9b i/o y10 pb6c pb7c pb9c i/o y11 pb6d pb7d pb9d i/o w11 peckb peckb peckb i-eckb v11 pb7b pb8b pb10b i/o u11 pb7c pb8c pb10c i/o pin or3t20 pad or3t30 pad or3t55 pad function select devices have been discontinued. see ordering information section for product status.
170 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas y12 pb7d pb8d pb10d i/o w12 pb8a pb9a pb11a i/o v12 pb8b pb9b pb11b i/o u12 pb8c pb9c pb11c i/o y13 pb8d pb9d pb11d i/o w13 pb9a pb10a pb12a i/o-hdc v13 pb9b pb10b pb12b i/o y14 pb9c pb10c pb12c i/o w14 pb9d pb10d pb12d i/o y15 pb10a pb11a pb13a i/o- ldc v14 pb10b pb11b pb13b i/o w15 pb10c pb11c pb13c i/o y16 pb10d pb11d pb13d i/o u14 pb12a pb14a i/o v15 pb12b pb14d i/o w16 pb11a pb12c pb15a i/o- init y17 pb15d i/o v16 pb12d pb16a i/o w17 pb11b pb13a pb16d i/o y18 pb11c pb13b pb17a i/o u16 pb11d pb13c pb17c i/o v17 pb12a pb13d pb17d i/o w18 pb12b pb14a pb18a i/o y19 pb12c pb14b pb18b i/o v18 pb12d pb14c pb18c i/o w19 pb14d pb18d i/o y20 pdone pdone pdone done w20 presetn presetn presetn reset v19 pprgmn pprgmn pprgmn prgm u19 pr12a pr14a pr18a i/o-m0 u18 pr14c pr18c i/o t17 pr14d pr18d i/o v20 pr13a pr17a i/o u20 pr12b pr13b pr17b i/o t18 pr12c pr13c pr17c i/o t19 pr12d pr13d pr17d i/o t20 pr11a pr12a pr16a i/o r18 pr11b pr12b pr16d i/o p17 pr11c pr12c pr15a i/o r19 pr11d pr12d pr15c i/o r20 pr10a pr11a pr15d i/o-m1 p18 pr10b pr11b pr14a i/o p19 pr10c pr11c pr14d i/o p20 pr10d pr11d pr13a i/o n18 pr9a pr10a pr12a i/o-m2 pin or3t20 pad or3t30 pad or3t55 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 171 data sheet november 2006 orca series 3c and 3t fpgas n19 pr9b pr10b pr12b i/o n20 pr9c pr10c pr12c i/o m17 pr9d pr10d pr12d i/o m18 pr8a pr9a pr11a i/o-m3 m19 pr8b pr9b pr11b i/o m20 pr8c pr9c pr11c i/o l19 pr8d pr9d pr11d i/o l18 pr7a pr8a pr10a i/o l20 pr7b pr8b pr10b i/o k20 pr7c pr8c pr10c i/o k19 pr7d pr8d pr10d i/o k18 peckr peckr peckr i-eckr k17 pr6b pr7b pr9b i/o j20 pr6c pr7c pr9c i/o j19 pr6d pr7d pr9d i/o j18 pr5a pr6a pr8a i/o j17 pr5b pr6b pr8b i/o h20 pr5c pr6c pr8c i/o h19 pr5d pr6d pr8d i/o h18 pr4a pr5a pr7a i/o-cs1 g20 pr4b pr5b pr7b i/o g19 pr4c pr5c pr7c i/o f20 pr4d pr5d pr7d i/o g18 pr3a pr4a pr6a i/o- cs0 f19 pr3b pr4b pr6b i/o e20 pr3c pr4c pr5b i/o g17 pr3d pr4d pr5d i/o f18 pr2a pr3a pr4a i/o-rd /mpi_strb e19 pr2b pr3b pr4b i/o d20 pr2c pr3c pr4d i/o e18 pr2d pr3d pr3a i/o d19 pr1a pr2a pr2a i/o- wr c20 pr1b pr2b pr2b i/o e17 pr1c pr2c pr2c i/o d18 pr1d pr2d pr2d i/o c19 pr1a pr1a i/o b20 pr1b pr1b i/o c18 pr1c pr1c i/o b19 pr1d pr1d i/o a20 prd_cfgn prd_cfgn prd_cfgn rd_cfg a19 pt12d pt14d pt18d i/o-seckur b18 pt14c pt18c i/o b17 pt12c pt14b pt18b i/o c17 pt12b pt14a pt18a i/o d16 pt12a pt13d pt17d i/o-rdy/rclk/mpi_ale a18 pt13c pt17a i/o pin or3t20 pad or3t30 pad or3t55 pad function select devices have been discontinued. see ordering information section for product status.
172 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas a17 pt11d pt13b pt16d i/o c16 pt11c pt13a pt16c i/o b16 pt11b pt12d pt16a i/o a16 pt11a pt12c pt15d i/o-d7 c15 pt12b pt15a i/o d14 pt10d pt12a pt14d i/o b15 pt10c pt11d pt14a i/o a15 pt10b pt11c pt13d i/o c14 pt10a pt11b pt13b i/o-d6 b14 pt9d pt11a pt13a i/o a14 pt9c pt10d pt12d i/o c13 pt10c pt12c i/o b13 pt9b pt10b pt12b i/o a13 pt9a pt10a pt12a i/o-d5 d12 pt8d pt9d pt11d i/o c12 pt8c pt9c pt11c i/o b12 pt8b pt9b pt11b i/o a12 pt8a pt9a pt11a i/o-d4 b11 peckt peckt peckt i-eckt c11 pt7c pt8c pt10c i/o a11 pt7b pt8b pt10b i/o a10 pt7a pt8a pt10a i/o-d3 b10 pt6d pt7d pt9d i/o c10 pt6c pt7c pt9c i/o d10 pt6b pt7b pt9b i/o a9 pt6a pt7a pt9a i/o-d2 b9 pt5d pt6d pt8d i/o-d1 c9 pt5c pt6c pt8c i/o d9 pt5b pt6b pt8b i/o a8 pt5a pt6a pt8a i/o-d0/din b8 pt4d pt5d pt7d i/o c8 pt4c pt5c pt7c i/o a7 pt4b pt5b pt7b i/o b7 pt4a pt5a pt7a i/o-dout a6 pt3d pt4d pt6d i/o c7 pt3c pt4c pt6a i/o b6 pt3b pt4b pt5c i/o a5 pt3a pt4a pt5a i/o-tdi d7 pt2d pt3d pt4d i/o c6 pt2c pt3c pt4a i/o b5 pt2b pt3b pt3d i/o a4 pt2a pt3a pt3a i/o-tms c5 pt2d pt2d i/o b4 pt1d pt2c pt2c i/o a3 pt1c pt2b pt2b i/o d5 pt1b pt2a pt2a i/o pin or3t20 pad or3t30 pad or3t55 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 173 data sheet november 2006 orca series 3c and 3t fpgas c4 pt1d pt1d i/o b3 pt1c pt1c i/o b2 pt1b pt1b i/o a2 pt1a pt1a pt1a i/o-tck c3 prd_data prd_data prd_data rd_data/tdo a1 v ss v ss v ss v ss d4 v ss v ss v ss v ss d8 v ss v ss v ss v ss d13 v ss v ss v ss v ss d17 v ss v ss v ss v ss h4 v ss v ss v ss v ss h17 v ss v ss v ss v ss n4 v ss v ss v ss v ss n17 v ss v ss v ss v ss u4 v ss v ss v ss v ss u8 v ss v ss v ss v ss u13 v ss v ss v ss v ss u17 v ss v ss v ss v ss j9 v ss v ss v ss v ss * j10 v ss v ss v ss v ss * j11 v ss v ss v ss v ss * j12 v ss v ss v ss v ss * k9 v ss v ss v ss v ss * k10 v ss v ss v ss v ss * k11 v ss v ss v ss v ss * k12 v ss v ss v ss v ss * l9 v ss v ss v ss v ss * l10 v ss v ss v ss v ss * l11 v ss v ss v ss v ss * l12 v ss v ss v ss v ss * m9 v ss v ss v ss v ss * m10 v ss v ss v ss v ss * m11 v ss v ss v ss v ss * m12 v ss v ss v ss v ss * d6 v dd v dd v dd v dd d11 v dd v dd v dd v dd d15 v dd v dd v dd v dd f4 v dd v dd v dd v dd f17 v dd v dd v dd v dd k4 v dd v dd v dd v dd l17 v dd v dd v dd v dd r4 v dd v dd v dd v dd r17 v dd v dd v dd v dd u6 v dd v dd v dd v dd u10 v dd v dd v dd v dd u15 v dd v dd v dd v dd pin or3t20 pad or3t30 pad or3t55 pad function select devices have been discontinued. see ordering information section for product status.
174 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas table 74. or3t55, or3c/t80, and or3t125 352-pin pbga pinout pin or3t55 pad or3c/t80 pad or3t125 pad function b1 pl1d pl1d pl1d i/o c2 pl1c pl1c pl1c i/o c1 pl1b pl1b pl1b i/o d2 pl1a pl1a pl1a i/o d3 pl2d pl2d pl2d i/o-a0/ mpi_be0 d1 pl2c pl2a pl2a i/o e2 pl2b pl3d pl3d i/o e4 pl3b pl3b i/o e3 pl2a pl3a pl3a i/o e1 pl3d pl4d pl4d i/o f2 pl3c pl4c pl4c i/o g4 pl3b pl4b pl4b i/o f3 pl3a pl4a pl5d i/o f1 pl4d pl5d pl6d i/o g2 pl4c pl5c pl6c i/o g1 pl4b pl5b pl6b i/o g3 pl4a pl5a pl7d i/o-a1/ mpi_be1 h2 pl5d pl6d pl8d i/o j4 pl5c pl6c pl8c i/o h1 pl5b pl6b pl8b i/o h3 pl5a pl6a pl8a i/o-a2 j2 pl6d pl7d pl9d i/o j1 pl6c pl7c pl9c i/o k2 pl6b pl7b pl9b i/o j3 pl6a pl7a pl9a i/o-a3 k1 pl7d pl8d pl10d i/o k4 pl7c pl8a pl10a i/o l2 pl7b pl9d pl11d i/o k3 pl7a pl9b pl11a i/o-a4 l1 pl8d pl9a pl12d i/o-a5 m2 pl8c pl10c pl12a i/o m1 pl8b pl10b pl13d i/o l3 pl8a pl10a pl13a i/o-a6 n2 peckl peckl peckl i-eckl m4 pl9c pl11c pl14c i/o n1 pl9b pl11b pl14b i/o m3 pl9a pl11a pl14a i/o-a7/mpi_clk p2 pl10d pl12d pl15d i/o p4 pl10c pl12c pl15c i/o p1 pl10b pl12b pl15b i/o n3 pl10a pl12a pl15a i/o-a8/mpi_rw r2 pl11d pl13d pl16d i/o-a9/ mpi_a ck p3 pl11c pl13b pl16a i/o r1 pl11b pl13a pl17d i/o t2 pl11a pl14c pl17a i/o-a10/ mpi_bi select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 175 data sheet november 2006 orca series 3c and 3t fpgas r3 pl12d pl14b pl18d i/o t1 pl12c pl15c pl18a i/o r4 pl12b pl15b pl19d i/o u2 pl12a pl15a pl19a i/o-a11/ mpi_irq t3 pl13d pl16d pl20d i/o-a12 u1 pl13c pl16c pl20c i/o u4 pl13b pl16b pl20b i/o v2 pl13a pl16a pl20a i/o u3 pl14d pl17d pl21d i/o v1 pl14c pl17c pl21c i/o w2 pl14b pl17b pl21b i/o-a13 w1 pl14a pl17a pl21a i/o v3 pl15d pl18d pl22d i/o y2 pl15c pl18c pl22c i/o w4 pl15b pl18b pl23d i/o y1 pl15a pl18a pl24d i/o w3 pl16d pl19d pl24a i/o-a14 aa2 pl16c pl19c pl25c i/o y4 pl16b pl19b pl25b i/o aa1 pl16a pl19a pl25a i/o y3 pl17d pl20d pl26d i/o ab2 pl17c pl20c pl26c i/o ab1 pl17b pl20a pl26a i/o aa3 pl17a pl21d pl27d i/o ac2 pl18d pl21c pl27c i/o ab4 pl18c pl21a pl27a i/o-seckll ac1 pl18b pl22d pl28d i/o ab3 pl22c pl28c i/o ad2 pl22b pl28b i/o ac3 pl18a pl22a pl28a i/o-a15 ad1 pcclk pcclk pcclk cclk af2 pb1a pb1a pb1a i/o-a16 ae3 pb1b pb1b i/o af3 pb1b pb1c pb1c i/o ae4 pb1c pb1d pb1d i/o ad4 pb1d pb2a pb2a i/o af4 pb2a pb2d pb2d i/o ae5 pb2b pb3a pb3a i/o ac5 pb2c pb3c pb3c i/o ad5 pb2d pb3d pb3d i/o af5 pb3a pb4a pb4a i/o ae6 pb3b pb4b pb4b i/o ac7 pb3c pb4c pb4c i/o ad6 pb3d pb4d pb4d i/o-a17 af6 pb4a pb5a pb5a i/o ae7 pb4b pb5b pb5b i/o pin or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
176 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas af7 pb4c pb5c pb5c i/o ad7 pb4d pb5d pb5d i/o ae8 pb5a pb6a pb6a i/o ac9 pb5b pb6b pb6d i/o af8 pb5c pb6c pb7a i/o ad8 pb5d pb6d pb7d i/o ae9 pb6a pb7a pb8a i/o af9 pb6b pb7b pb8d i/o ae10 pb6c pb7c pb9a i/o ad9 pb6d pb7d pb9d i/o af10 pb7a pb8a pb10a i/o ac10 pb7b pb8d pb10d i/o ae11 pb7c pb9a pb11a i/o ad10 pb7d pb9c pb11d i/o af11 pb8a pb9d pb12a i/o ae12 pb8b pb10a pb12d i/o af12 pb8c pb10b pb13a i/o ad11 pb8d pb10d pb13d i/o ae13 pb9a pb11a pb14a i/o ac12 pb9b pb11b pb14b i/o af13 pb9c pb11c pb14c i/o ad12 pb9d pb11d pb14d i/o ae14 peckb peckb peckb i-eckb ac14 pb10b pb12b pb15b i/o af14 pb10c pb12c pb15c i/o ad13 pb10d pb12d pb15d i/o ae15 pb11a pb13a pb16a i/o ad14 pb11b pb13b pb16d i/o af15 pb11c pb13c pb17a i/o ae16 pb11d pb14a pb17d i/o ad15 pb12a pb14b pb18a i/o-hdc af16 pb12b pb14d pb18d i/o ac15 pb12c pb15a pb19a i/o ae17 pb12d pb15d pb19d i/o ad16 pb13a pb16a pb20a i/o- ldc af17 pb13b pb16b pb20d i/o ac17 pb13c pb16c pb21a i/o ae18 pb13d pb16d pb21d i/o ad17 pb14a pb17a pb22a i/o af18 pb14b pb17b pb23a i/o ae19 pb14c pb17c pb23c i/o af19 pb14d pb17d pb23d i/o ad18 pb15a pb18a pb24a i/o- init ae20 pb15b pb18b pb24b i/o ac19 pb15c pb18c pb24c i/o af20 pb15d pb18d pb24d i/o pin or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 177 data sheet november 2006 orca series 3c and 3t fpgas ad19 pb16a pb19a pb25a i/o ae21 pb16b pb19b pb25b i/o ac20 pb16c pb19c pb25c i/o af21 pb16d pb19d pb25d i/o ad20 pb17a pb20a pb26a i/o ae22 pb17b pb20b pb26b i/o af22 pb17c pb20d pb26d i/o ad21 pb17d pb21a pb27a i/o ae23 pb21b pb27b i/o ac22 pb18a pb21d pb27d i/o af23 pb18b pb22a pb28a i/o ad22 pb18c pb22b pb28b i/o ae24 pb22c pb28c i/o ad23 pb18d pb22d pb28d i/o af24 pdone pdone pdone done ae26 presetn presetn presetn reset ad25 pprgmn pprgmn pprgmn prgm ad26 pr18a pr22a pr28a i/o-m0 ac25 pr18b pr22c pr28c i/o ac24 pr18c pr22d pr28d i/o ac26 pr18d pr21a pr27a i/o ab25 pr17a pr21d pr27d i/o ab23 pr17b pr20a pr26a i/o ab24 pr17c pr20b pr26b i/o ab26 pr17d pr20d pr26d i/o aa25 pr16a pr19a pr25a i/o y23 pr16b pr19b pr25b i/o aa24 pr16c pr19c pr25c i/o aa26 pr16d pr19d pr24a i/o y25 pr15a pr18a pr23a i/o y26 pr15b pr18b pr23b i/o y24 pr15c pr18c pr23d i/o w25 pr15d pr18d pr22d i/o-m1 v23 pr14a pr17a pr21a i/o w26 pr14b pr17b pr21b i/o w24 pr14c pr17c pr21c i/o v25 pr14d pr17d pr21d i/o v26 pr13a pr16a pr20a i/o u25 pr13b pr16b pr20b i/o v24 pr13c pr16c pr20c i/o u26 pr13d pr16d pr20d i/o u23 pr12a pr15a pr19a i/o-m2 t25 pr12b pr15d pr19d i/o u24 pr12c pr14a pr18a i/o t26 pr12d pr14c pr18d i/o r25 pr11a pr14d pr17a i/o-m3 pin or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
178 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas r26 pr11b pr13a pr17d i/o t24 pr11c pr13b pr16a i/o p25 pr11d pr13d pr16d i/o r23 pr10a pr12a pr15a i/o p26 pr10b pr12b pr15b i/o r24 pr10c pr12c pr15c i/o n25 pr10d pr12d pr15d i/o n23 peckr peckr peckr i-eckr n26 pr9b pr11b pr14b i/o p24 pr9c pr11c pr14c i/o m25 pr9d pr11d pr14d i/o n24 pr8a pr10a pr13a i/o m26 pr8b pr10c pr13d i/o l25 pr8c pr10d pr12a i/o m24 pr8d pr9b pr12d i/o l26 pr7a pr9c pr11a i/o-cs1 m23 pr7b pr9d pr11d i/o k25 pr7c pr8a pr10a i/o l24 pr7d pr8d pr10d i/o k26 pr6a pr7a pr9a i/o- cs0 k23 pr6b pr7b pr9b i/o j25 pr6c pr7c pr9c i/o k24 pr6d pr7d pr9d i/o j26 pr5a pr6a pr8a i/o h25 pr5b pr6b pr8b i/o h26 pr5c pr6c pr8c i/o j24 pr5d pr6d pr8d i/o g25 pr4a pr5a pr7a i/o- rd / mpi_strb h23 pr4b pr5b pr6a i/o g26 pr4c pr5c pr6c i/o h24 pr4d pr5d pr5a i/o f25 pr3a pr4a pr4a i/o g23 pr3b pr4b pr4b i/o f26 pr3c pr4c pr4c i/o g24 pr3d pr4d pr4d i/o e25 pr2a pr3a pr3a i/o- wr e26 pr2b pr3b pr3b i/o f24 pr3d pr3d i/o d25 pr2c pr2a pr2a i/o e23 pr2d pr2d pr2d i/o d26 pr1a pr1a pr1a i/o e24 pr1b pr1b pr1b i/o c25 pr1c pr1c pr1c i/o d24 pr1d pr1d pr1d i/o c26 prd_cfgn prd_cfgn prd_cfgn rd_cfg a25 pt18d pt22d pt28d i/o-seckur pin or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 179 data sheet november 2006 orca series 3c and 3t fpgas b24 pt18c pt22c pt28c i/o a24 pt22b pt28b i/o b23 pt18b pt22a pt28a i/o c23 pt18a pt21d pt27d i/o a23 pt17d pt21a pt27a i/o-rdy/rclk/ mpi_ale b22 pt17c pt20d pt26d i/o d22 pt17b pt20c pt26c i/o c22 pt17a pt20a pt26a i/o a22 pt16d pt19d pt25d i/o b21 pt16c pt19c pt25c i/o d20 pt16b pt19b pt25b i/o c21 pt16a pt19a pt25a i/o a21 pt15d pt18d pt24d i/o-d7 b20 pt15c pt18c pt24c i/o a20 pt15b pt18b pt24b i/o c20 pt15a pt18a pt24a i/o b19 pt14d pt17d pt23d i/o d18 pt14c pt17c pt23c i/o a19 pt14b pt17b pt23b i/o c19 pt14a pt17a pt22d i/o b18 pt13d pt16d pt21d i/o a18 pt13c pt16c pt21a i/o b17 pt13b pt16b pt20d i/o-d6 c18 pt13a pt16a pt20a i/o a17 pt12d pt15d pt19d i/o d17 pt12c pt15b pt19a i/o b16 pt12b pt15a pt18d i/o c17 pt12a pt14c pt18a i/o-d5 a16 pt11d pt14b pt17d i/o b15 pt11c pt13d pt17a i/o a15 pt11b pt13c pt16d i/o c16 pt11a pt13a pt16a i/o-d4 b14 peckt peckt peckt i-eckt d15 pt10c pt12c pt15c i/o a14 pt10b pt12b pt15b i/o c15 pt10a pt12a pt15a i/o-d3 b13 pt9d pt11d pt14d i/o d13 pt9c pt11c pt14c i/o a13 pt9b pt11b pt14b i/o c14 pt9a pt11a pt14a i/o-d2 b12 pt8d pt10d pt13d i/o-d1 c13 pt8c pt10b pt13a i/o a12 pt8b pt10a pt12d i/o b11 pt8a pt9c pt12a i/o-d0/din c12 pt7d pt9b pt11d i/o a11 pt7c pt8d pt11a i/o pin or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
180 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas d12 pt7b pt8c pt10d i/o b10 pt7a pt8a pt10a i/o-dout c11 pt6d pt7d pt9d i/o a10 pt6c pt7c pt9a i/o d10 pt6b pt7b pt8d i/o b9 pt6a pt7a pt8a i/o c10 pt5d pt6d pt7d i/o a9 pt5c pt6c pt7a i/o b8 pt5b pt6b pt6d i/o a8 pt5a pt6a pt6a i/o-tdi c9 pt4d pt5d pt5d i/o b7 pt4c pt5c pt5c i/o d8 pt4b pt5b pt5b i/o a7 pt4a pt5a pt5a i/o c8 pt3d pt4d pt4d i/o b6 pt3c pt4c pt4c i/o d7 pt3b pt4b pt4b i/o a6 pt3a pt4a pt4a i/o-tms c7 pt2d pt3d pt3d i/o b5 pt2c pt3a pt3a i/o a5 pt2b pt2d pt2d i/o c6 pt2c pt2c i/o b4 pt2b pt2b i/o d5 pt2a pt2a pt2a i/o a4 pt1d pt1d pt1d i/o c5 pt1c pt1c pt1c i/o b3 pt1b pt1b pt1b i/o c4 pt1a pt1a pt1a i/o-tck a3 prd_data prd_data prd_data rd_data/tdo a1 v ss v ss v ss v ss a2 v ss v ss v ss v ss a26 v ss v ss v ss v ss ac13 v ss v ss v ss v ss ac18 v ss v ss v ss v ss ac23 v ss v ss v ss v ss ac4 v ss v ss v ss v ss ac8 v ss v ss v ss v ss ad24 v ss v ss v ss v ss ad3 v ss v ss v ss v ss ae1 v ss v ss v ss v ss ae2 v ss v ss v ss v ss ae25 v ss v ss v ss v ss af1 v ss v ss v ss v ss af25 v ss v ss v ss v ss af26 v ss v ss v ss v ss pin or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 181 data sheet november 2006 orca series 3c and 3t fpgas b2 v ss v ss v ss v ss b25 v ss v ss v ss v ss b26 v ss v ss v ss v ss c24 v ss v ss v ss v ss c3 v ss v ss v ss v ss d14 v ss v ss v ss v ss d19 v ss v ss v ss v ss d23 v ss v ss v ss v ss d4 v ss v ss v ss v ss d9 v ss v ss v ss v ss h4 v ss v ss v ss v ss j23 v ss v ss v ss v ss n4 v ss v ss v ss v ss p23 v ss v ss v ss v ss v4 v ss v ss v ss v ss w23 v ss v ss v ss v ss l11 v ss v ss v ss v ss * l12 v ss v ss v ss v ss * l13 v ss v ss v ss v ss * l14 v ss v ss v ss v ss * l15 v ss v ss v ss v ss * l16 v ss v ss v ss v ss * m11 v ss v ss v ss v ss * m12 v ss v ss v ss v ss * m13 v ss v ss v ss v ss * m14 v ss v ss v ss v ss * m15 v ss v ss v ss v ss * m16 v ss v ss v ss v ss * n11 v ss v ss v ss v ss * n12 v ss v ss v ss v ss * n13 v ss v ss v ss v ss * n14 v ss v ss v ss v ss * n15 v ss v ss v ss v ss * n16 v ss v ss v ss v ss * p11 v ss v ss v ss v ss * p12 v ss v ss v ss v ss * p13 v ss v ss v ss v ss * p14 v ss v ss v ss v ss * p15 v ss v ss v ss v ss * p16 v ss v ss v ss v ss * r11 v ss v ss v ss v ss * r12 v ss v ss v ss v ss * r13 v ss v ss v ss v ss * r14 v ss v ss v ss v ss * r15 v ss v ss v ss v ss * pin or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
182 182 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas *thermally enhanced connection. r16 v ss v ss v ss v ss * t11 v ss v ss v ss v ss * t12 v ss v ss v ss v ss * t13 v ss v ss v ss v ss * t14 v ss v ss v ss v ss * t15 v ss v ss v ss v ss * t16 v ss v ss v ss v ss * aa23 v dd v dd v dd v dd aa4 v dd v dd v dd v dd ac11 v dd v dd v dd v dd ac16 v dd v dd v dd v dd ac21 v dd v dd v dd v dd ac6 v dd v dd v dd v dd d11 v dd v dd v dd v dd d16 v dd v dd v dd v dd d21 v dd v dd v dd v dd d6 v dd v dd v dd v dd f23 v dd v dd v dd v dd f4 v dd v dd v dd v dd l23 v dd v dd v dd v dd l4 v dd v dd v dd v dd t23 v dd v dd v dd v dd t4 v dd v dd v dd v dd pin or3t55 pad or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 183 data sheet november 2006 orca series 3c and 3t fpgas table 75. or3c/t80 and or3t125 432-pin ebga pinout pin or3c/t80 pad or3t125 pad function e4 prd_cfgn prd_cfgn rd_cfg d3 pr1d pr1d i/o d2 pr1c pr1c i/o d1 pr1b pr1b i/o f4 pr1a pr1a i/o e3 pr2d pr2d i/o e2 pr2c pr2c i/o e1 pr2b pr2b i/o f3 pr2a pr2a i/o f2 pr3d pr3d i/o f1 pr3c pr3c i/o h4 pr3b pr3b i/o g3 pr3a pr3a i/o- wr g2 pr4d pr4d i/o g1 pr4c pr4c i/o j4 pr4b pr4b i/o h3 pr4a pr4a i/o h2 pr5d pr5a i/o j3 pr5c pr6c i/o k4 pr5b pr6a i/o j2 pr5a pr7a i/o- rd / mpi_strb j1 pr6d pr8d i/o k3 pr6c pr8c i/o k2 pr6b pr8b i/o k1 pr6a pr8a i/o l3 pr7d pr9d i/o m4 pr7c pr9c i/o l2 pr7b pr9b i/o l1 pr7a pr9a i/o- cs0 m3 pr8d pr10d i/o n4 pr8a pr10a i/o m2 pr9d pr11d i/o n3 pr9c pr11a i/o-cs1 n2 pr9b pr12d i/o p4 pr9a pr12c i/o n1 pr10d pr12a i/o p3 pr10c pr13d i/o p2 pr10b pr13c i/o p1 pr10a pr13a i/o r3 pr11d pr14d i/o r2 pr11c pr14c i/o r1 pr11b pr14b i/o t2 peckr peckr i-eckr t4 pr12d pr15d i/o t3 pr12c pr15c i/o u1 pr12b pr15b i/o u2 pr12a pr15a i/o u3 pr13d pr16d i/o v1 pr13c pr16b i/o v2 pr13b pr16a i/o v3 pr13a pr17d i/o w1 pr14d pr17a i/o-m3 v4 pr14c pr18d i/o w2 pr14b pr18b i/o w3 pr14a pr18a i/o y2 pr15d pr19d i/o w4 pr15a pr19a i/o-m2 y3 pr16d pr20d i/o aa1 pr16c pr20c i/o aa2 pr16b pr20b i/o y4 pr16a pr20a i/o aa3 pr17d pr21d i/o ab1 pr17c pr21c i/o ab2 pr17b pr21b i/o ab3 pr17a pr21a i/o ac1 pr18d pr22d i/o-m1 ac2 pr18c pr23d i/o ab4 pr18b pr23b i/o ac3 pr18a pr23a i/o ad2 pr19d pr24a i/o ad3 pr19c pr25c i/o ac4 pr19b pr25b i/o ae1 pr19a pr25a i/o ae2 pr20d pr26d i/o ae3 pr20c pr26c i/o ad4 pr20b pr26b i/o af1 pr20a pr26a i/o af2 pr21d pr27d i/o af3 pr21c pr27c i/o ag1 pr21b pr27b i/o ag2 pr21a pr27a i/o ag3 pr22d pr28d i/o af4 pr22c pr28c i/o ah1 pr22b pr28b i/o ah2 pr22a pr28a i/o-m0 ah3 pprgmn pprgmn prgm ag4 presetn presetn reset ah5 pdone pdone done aj4 pb22d pb28d i/o ak4 pb22c pb28c i/o al4 pb22b pb28b i/o ah6 pb22a pb28a i/o aj5 pb21d pb27d i/o ak5 pb21c pb27c i/o al5 pb21b pb27b i/o aj6 pb21a pb27a i/o ak6 pb20d pb26d i/o al6 pb20c pb26c i/o pin or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
184 184 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas ah8 pb20b pb26b i/o aj7 pb20a pb26a i/o ak7 pb19d pb25d i/o al7 pb19c pb25c i/o ah9 pb19b pb25b i/o aj8 pb19a pb25a i/o ak8 pb18d pb24d i/o aj9 pb18c pb24c i/o ah10 pb18b pb24b i/o ak9 pb18a pb24a i/o- init al9 pb17d pb23d i/o aj10 pb17c pb23c i/o ak10 pb17b pb23a i/o al10 pb17a pb22a i/o aj11 pb16d pb21d i/o ah12 pb16c pb21a i/o ak11 pb16b pb20d i/o al11 pb16a pb20a i/o- ldc aj12 pb15d pb19d i/o ah13 pb15b pb19b i/o ak12 pb15a pb19a i/o aj13 pb14d pb18d i/o ak13 pb14c pb18b i/o ah14 pb14b pb18a i/o-hdc al13 pb14a pb17d i/o aj14 pb13d pb17b i/o ak14 pb13c pb17a i/o al14 pb13b pb16d i/o aj15 pb13a pb16a i/o ak15 pb12d pb15d i/o al15 pb12c pb15c i/o ak16 pb12b pb15b i/o ah16 peckb peckb i-eckb aj16 pb11d pb14d i/o al17 pb11c pb14c i/o ak17 pb11b pb14b i/o aj17 pb11a pb14a i/o al18 pb10d pb13d i/o ak18 pb10c pb13b i/o aj18 pb10b pb13a i/o al19 pb10a pb12d i/o ah18 pb9d pb12a i/o ak19 pb9c pb11d i/o aj19 pb9b pb11b i/o ak20 pb9a pb11a i/o ah19 pb8d pb10d i/o aj20 pb8b pb10b i/o al21 pb8a pb10a i/o pin or3c/t80 pad or3t125 pad function ak21 pb7d pb9d i/o ah20 pb7c pb9a i/o aj21 pb7b pb8d i/o al22 pb7a pb8a i/o ak22 pb6d pb7d i/o aj22 pb6c pb7a i/o al23 pb6b pb6d i/o ak23 pb6a pb6a i/o ah22 pb5d pb5d i/o aj23 pb5c pb5c i/o ak24 pb5b pb5b i/o aj24 pb5a pb5a i/o ah23 pb4d pb4d i/o-a17 al25 pb4c pb4c i/o ak25 pb4b pb4b i/o aj25 pb4a pb4a i/o ah24 pb3d pb3d i/o al26 pb3c pb3c i/o ak26 pb3b pb3b i/o aj26 pb3a pb3a i/o al27 pb2d pb2d i/o ak27 pb2c pb2c i/o aj27 pb2b pb2b i/o ah26 pb2a pb2a i/o al28 pb1d pb1d i/o ak28 pb1c pb1c i/o aj28 pb1b pb1b i/o ah27 pb1a pb1a i/o-a16 ag28 pcclk pcclk cclk ah29 pl22a pl28a i/o-a15 ah30 pl22b pl28b i/o ah31 pl22c pl28c i/o af28 pl22d pl28d i/o ag29 pl21a pl27a i/o-seckll ag30 pl21b pl27b i/o ag31 pl21c pl27c i/o af29 pl21d pl27d i/o af30 pl20a pl26a i/o af31 pl20b pl26b i/o ad28 pl20c pl26c i/o ae29 pl20d pl26d i/o ae30 pl19a pl25a i/o ae31 pl19b pl25b i/o ac28 pl19c pl25c i/o ad29 pl19d pl24a i/o-a14 ad30 pl18a pl24d i/o ac29 pl18b pl23d i/o ab28 pl18c pl22c i/o pin or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 185 data sheet november 2006 orca series 3c and 3t fpgas ac30 pl18d pl22d i/o ac31 pl17a pl21a i/o ab29 pl17b pl21b i/o-a13 ab30 pl17c pl21c i/o ab31 pl17d pl21d i/o aa29 pl16a pl20a i/o y28 pl16b pl20b i/o aa30 pl16c pl20c i/o aa31 pl16d pl20d i/o-a12 y29 pl15a pl19a i/o-a11/ mpi_irq w28 pl15b pl19d i/o y30 pl15c pl18a i/o w29 pl14a pl18c i/o w30 pl14b pl18d i/o v28 pl14c pl17a i/o-a10/ mpi_bi w31 pl14d pl17c i/o v29 pl13a pl17d i/o v30 pl13b pl16a i/o v31 pl13c pl16c i/o u29 pl13d pl16d i/o-a9/ mpi_a ck u30 pl12a pl15a i/o-a8/mpi_rw u31 pl12b pl15b i/o t30 pl12c pl15c i/o t28 pl12d pl15d i/o t29 pl11a pl14a i/o-a7/mpi_clk r31 pl11b pl14b i/o r30 pl11c pl14c i/o r29 peckl peckl i-eckl p31 pl10a pl13a i/o-a6 p30 pl10b pl13d i/o p29 pl10c pl12a i/o n31 pl10d pl12c i/o p28 pl9a pl12d i/o-a5 n30 pl9b pl11a i/o-a4 n29 pl9c pl11c i/o m30 pl9d pl11d i/o n28 pl8a pl10a i/o m29 pl8c pl10c i/o l31 pl8d pl10d i/o l30 pl7a pl9a i/o-a3 m28 pl7b pl9b i/o l29 pl7c pl9c i/o k31 pl7d pl9d i/o k30 pl6a pl8a i/o-a2 k29 pl6b pl8b i/o j31 pl6c pl8c i/o j30 pl6d pl8d i/o k28 pl5a pl7d i/o-a1/ mpi_be1 j29 pl5b pl6b i/o h30 pl5c pl6c i/o pin or3c/t80 pad or3t125 pad function h29 pl5d pl6d i/o j28 pl4a pl5d i/o g31 pl4b pl4b i/o g30 pl4c pl4c i/o g29 pl4d pl4d i/o h28 pl3a pl3a i/o f31 pl3b pl3b i/o f30 pl3c pl3c i/o f29 pl3d pl3d i/o e31 pl2a pl2a i/o e30 pl2b pl2b i/o e29 pl2c pl2c i/o f28 pl2d pl2d i/o-a0/ mpi_be0 d31 pl1a pl1a i/o d30 pl1b pl1b i/o d29 pl1c pl1c i/o e28 pl1d pl1d i/o d27 prd_data prd_data rd_data/tdo c28 pt1a pt1a i/o-tck b28 pt1b pt1b i/o a28 pt1c pt1c i/o d26 pt1d pt1d i/o c27 pt2a pt2a i/o b27 pt2b pt2b i/o a27 pt2c pt2c i/o c26 pt2d pt2d i/o b26 pt3a pt3a i/o a26 pt3b pt3b i/o d24 pt3c pt3c i/o c25 pt3d pt3d i/o b25 pt4a pt4a i/o-tms a25 pt4b pt4b i/o d23 pt4c pt4c i/o c24 pt4d pt4d i/o b24 pt5a pt5a i/o c23 pt5b pt5b i/o d22 pt5c pt5c i/o b23 pt5d pt5d i/o a23 pt6a pt6a i/o-tdi c22 pt6b pt6d i/o b22 pt6c pt7a i/o a22 pt6d pt7d i/o c21 pt7a pt8a i/o d20 pt7b pt8d i/o b21 pt7c pt9a i/o a21 pt7d pt9d i/o c20 pt8a pt10a i/o-dout d19 pt8c pt10d i/o b20 pt8d pt11a i/o c19 pt9a pt11c i/o pin or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
186 186 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas b19 pt9b pt11d i/o d18 pt9c pt12a i/o-d0/din a19 pt9d pt12c i/o c18 pt10a pt12d i/o b18 pt10b pt13a i/o a18 pt10c pt13c i/o c17 pt10d pt13d i/o-d1 b17 pt11a pt14a i/o-d2 a17 pt11b pt14b i/o b16 pt11c pt14c i/o d16 pt11d pt14d i/o c16 pt12a pt15a i/o-d3 a15 pt12b pt15b i/o b15 pt12c pt15c i/o c15 peckt peckt i-eckt a14 pt13a pt16a i/o-d4 b14 pt13b pt16b i/o c14 pt13c pt16d i/o a13 pt13d pt17a i/o d14 pt14a pt17b i/o b13 pt14b pt17d i/o c13 pt14c pt18a i/o-d5 b12 pt14d pt18b i/o d13 pt15a pt18d i/o c12 pt15b pt19a i/o a11 pt15d pt19d i/o b11 pt16a pt20a i/o d12 pt16b pt20d i/o-d6 c11 pt16c pt21a i/o a10 pt16d pt21d i/o b10 pt17a pt22d i/o c10 pt17b pt23b i/o a9 pt17c pt23c i/o b9 pt17d pt23d i/o d10 pt18a pt24a i/o c9 pt18b pt24b i/o b8 pt18c pt24c i/o c8 pt18d pt24d i/o-d7 d9 pt19a pt25a i/o a7 pt19b pt25b i/o b7 pt19c pt25c i/o c7 pt19d pt25d i/o d8 pt20a pt26a i/o a6 pt20b pt26b i/o b6 pt20c pt26c i/o c6 pt20d pt26d i/o a5 pt21a pt27a i/o-rdy/rclk/mpi_ale b5 pt21b pt27b i/o c5 pt21c pt27c i/o d6 pt21d pt27d i/o pin or3c/t80 pad or3t125 pad function a4 pt22a pt28a i/o b4 pt22b pt28b i/o c4 pt22c pt28c i/o d5 pt22d pt28d i/o-seckur a12 v ss v ss v ss a16 v ss v ss v ss a2 v ss v ss v ss a20 v ss v ss v ss a24 v ss v ss v ss a29 v ss v ss v ss a3 v ss v ss v ss a30 v ss v ss v ss a8 v ss v ss v ss ad1 v ss v ss v ss ad31 v ss v ss v ss aj1 v ss v ss v ss aj2 v ss v ss v ss aj30 v ss v ss v ss aj31 v ss v ss v ss ak1 v ss v ss v ss ak29 v ss v ss v ss ak3 v ss v ss v ss ak31 v ss v ss v ss al12 v ss v ss v ss al16 v ss v ss v ss al2 v ss v ss v ss al20 v ss v ss v ss al24 v ss v ss v ss al29 v ss v ss v ss al3 v ss v ss v ss al30 v ss v ss v ss al8 v ss v ss v ss b1 v ss v ss v ss b29 v ss v ss v ss b3 v ss v ss v ss b31 v ss v ss v ss c1 v ss v ss v ss c2 v ss v ss v ss c30 v ss v ss v ss c31 v ss v ss v ss h1 v ss v ss v ss h31 v ss v ss v ss m1 v ss v ss v ss m31 v ss v ss v ss t1 v ss v ss v ss t31 v ss v ss v ss y1 v ss v ss v ss y31 v ss v ss v ss a1 v dd v dd v dd a31 v dd v dd v dd pin or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 187 data sheet november 2006 orca series 3c and 3t fpgas aa28 v dd v dd v dd aa4 v dd v dd v dd ae28 v dd v dd v dd ae4 v dd v dd v dd ah11 v dd v dd v dd ah15 v dd v dd v dd ah17 v dd v dd v dd ah21 v dd v dd v dd ah25 v dd v dd v dd ah28 v dd v dd v dd ah4 v dd v dd v dd ah7 v dd v dd v dd aj29 v dd v dd v dd aj3 v dd v dd v dd ak2 v dd v dd v dd ak30 v dd v dd v dd al1 v dd v dd v dd al31 v dd v dd v dd b2 v dd v dd v dd b30 v dd v dd v dd c29 v dd v dd v dd c3 v dd v dd v dd d11 v dd v dd v dd d15 v dd v dd v dd d17 v dd v dd v dd d21 v dd v dd v dd d25 v dd v dd v dd d28 v dd v dd v dd d4 v dd v dd v dd d7 v dd v dd v dd g28 v dd v dd v dd g4 v dd v dd v dd l28 v dd v dd v dd l4 v dd v dd v dd r28 v dd v dd v dd r4 v dd v dd v dd u28 v dd v dd v dd u4 v dd v dd v dd pin or3c/t80 pad or3t125 pad function select devices have been discontinued. see ordering information section for product status.
188 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas package thermal characteristics there are four thermal parameters that are in common use: ja , jc, jc, and jb . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system air?w. table 76 contains the currently available thermal speci?ations for fpga packages mounted on both jedec and non-jedec test boards. the thermal values for the newer package types correspond to those packages mounted on a jedec four-layer board. the values for the older packages, however, correspond to those packages mounted on a non-jedec, single-layer, sparse copper board (see note 2). it should also be noted that the values for the older packages are considered conservative. ? ? ja this is the thermal resistance from junction to ambient (a.k.a. theta-ja, r-theta, etc.). where t j is the junction temperature, t a is the ambient air temperature, and q is the chip power. experimentally, ja is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced con- vection measurements. a controlled amount of power (q) is dissipated in the test chips heater resistor, the chips temperature (t j ) is determined by the forward drop on the diodes, and the ambient temperature (t a ) is noted. note that ja is expressed in units of ?/watt. ja t j t a q ------------------- - = select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 189 data sheet november 2006 orca series 3c and 3t fpgas ? ? jc this jedec designated parameter correlates the junction temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true ther- mal resistance, and it is de?ed by: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. dur- ing the ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. jc is also expressed in units of ?/watt. ? ? jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is de?ed by: the parameters in this equation have been de?ed above. however, the measurements are performed with the case of the part pressed against a water-cooled heat sink so as to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates jc from jc. jc is a true thermal resistance and is expressed in units of ?/watt. jb this is the thermal resistance from junction to board (a.k.a. jl ). it is de?ed by: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other parameters on the right-hand side have been de?ed above. this is considered a true thermal resistance, and the measure- ment is made with a water-cooled heat sink pressed against the board so as to draw most of the heat out of the leads. note that jb is expressed in units of ?/watt, and that this parameter and the way it is measured is still in jedec committee. jc t j t c q -------------------- = jc t j t c q -------------------- = jb t j t b q ------------------- - = select devices have been discontinued. see ordering information section for product status.
190 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas package thermal characteristics (continued) fpga maximum junction temperature once the power dissipated by the fpga has been determined (see the estimating power dissipation section), the maximum junction temperature of the fpga can be found. this is needed to determine if speed derating of the device from the 85 ? junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in ?), the maximum junction tempera- ture is approximated by: t jmax = t amax + (q ? ja ) table 76 lists the plastic package thermal characteristics for the orca series fpgas. table 76. plastic package thermal characteristics for the orca series 1 1. mounted on 4-layer jedec standard test board with two power/ground planes. 2. with thermal balls connected to board ground plane. 3. without thermal balls connected to board ground plane. package ja (?/w) t a = 70 ? max t j = 125 ? max @ 0 fpm (w) 0 fpm 200 fpm 500 fpm 144-pin tqfp 1 52.0 39.0 1.1 208-pin sqfp 1 26.5 23.0 21.0 2.1 208-pin sqfp2 1 12.8 10.3 9.1 4.3 240-pin sqfp 1 25.5 22.5 21.0 2.2 240-pin sqfp2 1 13.0 10.0 9.0 4.2 256-pin pbga 1, 2 22.5 19.0 17.5 2.4 256-pin pbga 1, 3 26.0 22.0 20.5 2.1 352-pin pbga 1, 2 19.0 16.0 15.0 2.9 352-pin pbga 1, 3 25.5 22.0 20.5 2.1 432-pin ebga 1 11.0 8.5 7.5 5.0 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 191 data sheet november 2006 orca series 3c and 3t fpgas package coplanarity the coplanarity limits of the orca series 3 packages are as follows. table 77. package coplanarity package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 78 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capacitance of the lead to the near- est neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. the lead resistance value, r w , is in m . the parasitic values in table 78 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designers model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. table 78. package parasitics package type coplanarity limit (mils) ebga 8.0 pbga 8.0 sqfp/sqfp2 4.0 3.15 tqfp 3.15 package type l sw l mw r w c 1 c 2 c m l sl l ml 144-pin tqfp 3 1 140 1 1 0.6 4? 2?.5 208-pin sqfp 4 2 200 1 1 1 7?0 4? 208-pin sqfp2 4 2 200 1 1 1 6? 4? 240-pin sqfp 4 2 200 1 1 1 8?2 5? 240-pin sqfp2 4 2 200 1 1 1 7?1 4? 256-pin pbga 5 2 220 1 1 1 5? 2? 352-pin pbga 5 2 220 1.5 1.5 1.5 7?2 3? 432-pin ebga 4 1.5 500 1 1 0.3 3?.5 0.5? select devices have been discontinued. see ordering information section for product status.
192 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas 5-3862(f).a figure 104. package parasitics package outline diagrams terms and denitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for ? and tolerance. typical (typ): when speci?d after a dimension, this indicates the repeated design size if a tolerance is speci?d or repeated basic size if a tolerance is not speci?d. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension. pad n board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 pad n + 1 l sw r w l sl select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 193 data sheet november 2006 orca series 3c and 3t fpgas package outline diagrams (continued) 144-pin tqfp dimensions are in millimeters. detail b 0.19/0.27 0.08 m 0.106/0.200 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 1.60 max seating plane 0.08 0.50 typ 1.40 0.05 0.05/0.15 detail a detail b pin #1 identifier zone 20.00 0.20 22.00 0.20 109 144 1 36 37 72 73 108 20.00 0.20 22.00 0.20 select devices have been discontinued. see ordering information section for product status.
194 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas package outline diagrams (continued) 208-pin sqfp dimensions are in millimeters. note: the dimensions in this outline diagram are intended for informational purposes only. 156 105 30.60 ?0.20 157 208 1 52 53 104 28.00 ?0.20 28.00 ?0.20 30.60 ?0.20 pin #1 identifier zone 4.10 max 0.08 3.40 ?0.20 seating plane 0.25 min 0.50 typ detail b detail a 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200 select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 195 data sheet november 2006 orca series 3c and 3t fpgas package outline diagrams (continued) 208-pin sqfp2 dimensions are in millimeters. detail c (sqfp2 chip-up) 5-3828(f).a 5-3828(f) chip chip bonded face up copper heat sink 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.2 0.1 0 m 0.090/0.200 156 105 30.60 0.20 157 208 53 104 28.00 0.20 exposed heat sink appears on bottom surface: chip bonded face up. (see detail c.) 28.00 0.20 30.60 0.20 pin #1 identifier zone 21.0 ref 21.0 ref 4.10 max 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail b detail a select devices have been discontinued. see ordering information section for product status.
196 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas package outline diagrams (continued) 240-pin sqfp dimensions are in millimeters. note: the dimensions in this outline diagram are intended for informational purposes only. 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200 180 121 181 240 34.60 ?0.20 1 32.00 ?0.20 60 61 120 pin #1 identifier zone 32.00 ?0.20 34.60 ?0.20 0.08 3.40 ?0.20 s eating pla ne 0.25 min 0.50 typ detail a detail b 4.10 max select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 197 data sheet november 2006 orca series 3c and 3t fpgas package outline diagrams (continued) 240-pin sqfp2 dimensions are in millimeters. detail c (sqfp2 chip-up) 5-3825(f).a 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200 chip chip bonded face up copper heat sink 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail a detail b 180 121 181 240 34.60 0.20 1 32.00 0.20 60 61 120 pin # 1 identi fier zone 32.00 0.20 34.60 0.20 exposed heat sink appears on bottom surface: chip bonded face up. (see detail c.) 24 .2 re f 24. 2 ref 4.10 max select devices have been discontinued. see ordering information section for product status.
198 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas package outline diagrams (continued) 256-pin pbga dimensions are in millimeters. 5-4406(f) note: although the 16 thermal enhancement balls are stated as an option, they are standard on the 256 fpga package. 0.36 0.04 1.17 0.05 2.13 0.19 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 27.00 0.20 27.00 0.20 24.00 +0.70 ?.00 24.00 +0.70 ?.00 a1 ball identifier zone a b c d e f g h j k l m y n p r t u v w 12345678910 11 12 13 14 15 16 17 18 20 19 center array for thermal enhancement (optional) 19 spaces @ 1.27 = 24.13 a1 ball corner 19 spaces @ 1.27 = 24.13 0.75 0.15 (see note below) select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 199 data sheet november 2006 orca series 3c and 3t fpgas package outline diagrams (continued) 352-pin pbga dimensions are in millimeters. 5-4407(f) note: although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 fpga package. 0.56 0.06 1.17 0.05 2.33 0.21 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 35.00 +0.70 ?.00 30.00 a1 ball identifier zone af ae ad ac ab aa y w v u t r g 25 spaces @ 1.27 = 31.75 p n m l k j h 12345678910 12 14 16 18 22 24 26 20 11 13 15 17 2119 23 25 f e d c b a center array 25 spaces a1 ball 0.75 0.15 35.00 0.20 30.00 +0.70 ?.00 0.20 @ 1.27 = 31.75 for thermal enhancement (optional) corner (see note below) select devices have been discontinued. see ordering information section for product status.
200 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas package outline diagrams (continued) 432-pin ebga dimensions are in millimeters. 5-4409(f) 0.91 0.06 1.54 0.13 seating plane solder ball 0.63 0.07 0.20 40.00 0.10 40.00 a1 ball m d ag b f k h g e ad l t j n aj c y p ah ae ac aa w u r ak af ab v al a 19 30 26 5 28 2422 23 25 7 20 3129 15 21 18 32 7 11 17 4 6 8 10 12 14 16 2 913 1 30 spaces @ 1.27 = 38.10 30 spaces a1 ball 0.75 0.15 identifier zone 0.10 @ 1.27 = 38.10 corner select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 201 data sheet november 2006 orca series 3c and 3t fpgas ordering information table 79. ordering information commercial device family part number speed grade package type pin/ball count grade packing designator or3c80 or3c805ps208-db 2 5 sqfp2 208 c db or3c805ba352-db 2 5 pbga 352 c db or3c804ps208-db 2 4 sqfp2 208 c db or3c804ba352-db 2 4 pbga 352 c db or3t20 or3t207s208-db 7 sqfp 208 c db or3t207ba256-db 7 pbga 256 c db or3t206s208-db 6 sqfp 208 c db or3t206t144-db 6 tqfp 144 c db or3t206ba256-db 6 pbga 256 c db or3t30 or3t307s208-db 7 sqfp 208 c db or3t307s240-db 7 sqfp 240 c db or3t307ba256-db 7 pbga 256 c db or3t306s208-db 6 sqfp 208 c db or3t306s240-db 6 sqfp 240 c db or3t306ba256-db 6 pbga 256 c db device family or3t20 or3t30 or3t55 or3c80 or3t80 or3t125 or3xxxx x x xx xx xxx packing designator db = dry packed tray speed grade package type ba = plastic ball grid array (pbga) bc = enhanced ball grid array (ebga) ps = power quad shrink flat package (sqfp2) s = shrink quad flat package (sqfp) t = thin quad flat package (tqfp) pin/ball count grade blank = commercial i = industrial select devices have been discontinued. see ordering information section for product status.
202 lattice semiconductor data sheet november 2006 orca series 3c and 3t fpgas or3t55 or3t557ps208-db 1 7 sqfp2 208 c db or3t557s208-db 7 sqfp 208 c db or3t557ps240-db 3 7 sqfp2 240 c db or3t557ba256-db 7 pbga 256 c db or3t557ba352-db 7 pbga 352 c db or3t556ps208-db 1 6 sqfp2 208 c db or3t556s208-db 6 sqfp 208 c db or3t556ps240-db 3 6 sqfp2 240 c db or3t556ba256-db 6 pbga 256 c db or3t556ba352-db 6 pbga 352 c db or3t80 or3t807ps208-db 1 7 sqfp2 208 c db or3t807s208-db 7 sqfp 208 c db or3t807ps240-db 3 7 sqfp2 240 c db or3t807ba352-db 7 pbga 352 c db or3t807bc432-db 7 ebga 432 c db or3t806ps208-db 1 6 sqfp2 208 c db or3t806s208-db 6 sqfp 208 c db or3t806ps240-db 3 6 sqfp2 240 c db or3t806ba352-db 6 pbga 352 c db or3t806bc432-db 6 ebga 432 c db or3t125 or3t1257ps208-db 3 7 sqfp2 208 c db or3t1257ps240-db 3 7 sqfp2 240 c db or3t1257ba352-db 7 pbga 352 c db or3t1257bc432-db 7 ebga 432 c db or3t1256ps208-db 3 6 sqfp2 208 c db or3t1256ps240-db 3 6 sqfp2 240 c db or3t1256ba352-db 6 pbga 352 c db or3t1256bc432-db 6 ebga 432 c db commercial device family part number speed grade package type pin/ball count grade packing designator select devices have been discontinued. see ordering information section for product status.
lattice semiconductor 203 data sheet november 2006 orca series 3c and 3t fpgas industrial 1. converted to s208 package device per pcn#11a-06. 2. discontinued per pcn#02-06. contact rochester electronics for available inventory. 2. discontinued per pcn#06-07. contact rochester electronics for available inventory. device family part number speed grade package type pin/ball count grade packing designator or3c80 or3c804ps208i-db 2 4 sqfp2 208 i db OR3C804BA352I-DB 2 4 pbga 352 i db or3t20 or3t206s208i-db 6 sqfp 208 i db or3t30 or3t306s208i-db 6 sqfp 208 i db or3t306s240i-db 6 sqfp 240 i db or3t306ba256i-db 6 pbga 256 i db or3t55 or3t556ps208i-db 1 6 sqfp2 208 i db or3t556s208i-db 6 sqfp 208 i db or3t556ps240i-db 3 6 sqfp2 240 i db or3t556ba256i-db 6 pbga 256 i db or3t556ba352i-db 6 pbga 352 i db or3t80 or3t806ps208i-db 1 6 sqfp2 208 i db or3t806s208i-db 6 sqfp 208 i db or3t806ps240i-db 3 6 sqfp2 240 i db or3t806ba352i-db 6 pbga 352 i db or3t806bc432i-db 6 ebga 432 i db or3t125 or3t1256ps208i-db 3 6 sqfp2 208 i db or3t1256ps240i-db 3 6 sqfp2 240 i db or3t1256ba352i-db 6 pbga 352 i db or3t1256bc432i-db 6 ebga 432 i db select devices have been discontinued. see ordering information section for product status.

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